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FLI2200 rev. 1.04, 1/19/01 2 company confidential ? 2000-2001 faroudja labs, inc.
table of contents description and features ............................................................................................................................... ............. 3 simplified block diagram ....................................................................................................... ..................................... 4 packaging and pinout information ............................................................................................................................ 4 pin connections and functions ............................................................................................................................... . 5 descriptions of functional blocks ............................................................................................................................ 9 memory map ............................................................................................................................... ............................... 11 register details ............................................................................................................................... ........................... 13 control bus operation and control protocol ........................................................................................................ 41 electrical characteristics ............................................................................................................................... ............ 43 input and output signal timing .............................................................................................................................. 44 applications information ............................................................................................................................... .......... 46 interfacing to the fli2000 decoder (or other decoder with itu-r bt656 output) .......................................... 48 input modes and busses ............................................................................................................................... .......... 49 output modes and busses ............................................................................................................................... ....... 50 package dimensions ............................................................................................................................... ................. 51
? 2000-2001 faroudja labs, inc. company confidential 3 rev. 1.04, 1/19/01 FLI2200 description the FLI2200 is a single chip implementation of faroudja laboratories? award winning deinterlacing and post- processing algorithms that produce the highest quality progressive video output from a variety of interlaced video inputs including 525/60 (ntsc) or 625/50 (pal or secam). it uses patented and patent pending motion-adaptive deinterlacing that selects the optimal filtering on a per-pixel basis. this includes detection and proper interleaving of 3:2 and 2:2 pulldown for film-base sources, including continuous monitoring and compensation for bad edits that occur frequently in broadcast material due to poor scene cuts or insertion of commercials. video material is processed by a set of content-sensitive spatio-temporal filters that adapt to the appropriate direction for smoothest interpolation using the patented faroudja dcdi? algorithm. the FLI2200 also includes motion-adaptive cross-color suppression that removes highly objectionable coloration artifacts produced by commonly used video decoders. its internal processing uses 10 bits per channel to maintain the highest quality. its inputs and outputs are 10 bits/channel for best quality but also supports 8 bits/channel for more cost-sensitive applications. the FLI2200 requires 4 mb of low cost sdram for best quality deinterlacing, but it can also be operated in an optimized intra-field mode without memory for more cost- sensitive applications. this makes possible the use of a single design for both high-end and low-end applications. the FLI2200 integrates a number of functions to provide maximum flexibility in a low cost configuration. this includes an on-chip clock generator, sdram controller, display controller, input and output color-space converters. it uses a standard 2-wire serial control interface for easy control and access to the registers. the FLI2200 can be connected without glue logic to the fli2000 video decoder and fli2220 enhancer and osd generator to produce the highest quality video pipeline for premium applications. it is also fully compatible with other decoders having a itu-r bt 656 output format. applications flat panel tv ? lcd, pdp progressive scan tvs multimedia front/rear projectors home theater scan converters multimedia pcs/workstations dcdi? is a faroudja trademark features motion-adaptive cross-color suppression removes artifacts produced by improper y/c separation in low- cost video decoders motion-adaptive video deinterlacing selects optimal filtering on a per-pixel basis film-mode for proper handling of 3:2 and 2:2 pulldown material bad-edit detection/correction compensates for poor scene cuts and insertions common in broadcast material motion-weighted interpolation for video sources produces maximum resolution without introducing motion artifacts directional correlational deinterlacing (dcdi?) minimizes jaggies on angled lines 8/10-bit y/cb/cr (d1) (itu-r bt 656), 16/20-bit y cb/cr (itu-r bt 601), 24/30-bit rgb or ycbcr/ypbpr interlaced input options supports 525/60 (ntsc), 625/50 (pal/secam) accepts up to 1100 pixels/line 8/10-bit, 16/20-bit yuv, 24/30-bit rgb or ycbcr/ypbpr progressive output options supports 8- or 10-bit inputs and outputs 10-bit internal processing for highest quality includes color-space converters at input and output for maximum flexibility auto-detection of ntsc/pal/secam inputs high-order filtering produces smooth chroma output in 4:2:2 to 4:4:4 or 4:4:4 to 4:2:2 conversions resolution recovery maximizes output signal-to-noise ratio and dynamic range can be operated without glue logic with fli2000 video decoder and fli2220 enhancer and osd generator ics to produce highest quality video pipeline glue-less interface to most standard video decoders built-in display timing generator on-chip clock generator eliminates external plls on-chip sdram controller uses low cost sdram as field memory ? 4 mb optimized intra-field operation allows memory-less configuration for lowest cost applications with same design and layout as for high-end applications 2-wire serial control interface for easy control 176-pin tqfp package

FLI2200 rev. 1.04, 1/19/01 4 company confidential ? 2000-2001 faroudja labs, inc. package: 176-pin tqfp. ja = xx c/watt packaging and pinout information simplified block diagram 10 rgb /yuv/ yc rc b /d 1 input signal formatter output signal formatter ext. syncs sync generator yu v/ rgb/ yc rc b sync out 10 control interface and registers scl sda pixclk pll/clock generator daddr 2 deinterlacer core with dcdi?, motion compensation,film mode detection and bad edit correction 10 rgb /yuv/ yc rc b /d 1 input signal formatter output signal formatter ext. syncs sync generator yu v/ rgb/ yc rc b sync out 10 control interface and registers scl sda pixclk pll/clock generator daddr 2 deinterlacer core with dcdi?, motion compensation,film mode detection and bad edit correction data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 data16 data17 data18 data19 data20 vdd33 vss vdd33 vss data21 data22 data23 data24 data25 data26 data27 data28 data29 vdd33 vss addr3 addr2 addr1 addr0 vdd25 vss data0 data1 data2 data3 data4 hsyncrefi vsyncrefi 1 10 20 30 40 50 60 70 80 130 120 110 100 90 140 150 160 170 vdd33 vss b/cbin0 b/cbin1 b/cbin2 b/cbin3 b/cbin4 b/cbin5 b/cbin6 b/cbin7 b/cbin8 b/cbin9 fieldin vdd25 vss g/yin0 g/yin1 g/yin2 g/yin3 g/yin4 g/yin5 g/yin6 g/yin7 g/yin8 g/yin9 r/crin0 r/crin1 r/crin2 r/crin3 r/crin4 r/crin5 r/crin6 r/crin7 r/crin8 r/crin9 vdd33 vss pixclk test0 daddr1 avdd avss test1 test2 nomem oe iformat2 iformat1 iformat0 oformat2 oformat1 oformat0 n/p/in/out vdd33 vss vdd33 vss g/yout9 g/yout8 g/yout7 g/yout6 g/yout5 g/yout4 g/yout3 g/yout2 g/yout1 g/yout0 vdd33 vss r/crout9 r/crout8 r/crout7 r/crout6 r/crout5 r/crout4 r/crout3 r/crout2 r/crout1 r/crout0 vrefo hrefo vdd25 vss vsync/crefo h/csynco b/cbout9 b/cbout8 b/cbout7 b/cbout6 b/cbout5 b/cbout4 b/cbout3 b/cbout2 b/cbout1 b/cbout0 vdd33 vss vdd25 vss test3 test4 film test5 testo1 testo0 vdd33 vss cclko yclko memclko wen rasn casn vdd33 vss daddr0 mode sda scl resetb vdd33 vss bsel vdd33 vss addr10 addr9 addr8 addr7 addr6 addr5 addr4
? 2000-2001 faroudja labs, inc. company confidential 5 rev. 1.04, 1/19/01 FLI2200 pin connections and functions pin # name description power supply connections (not shown on block diagram) see list v ss ground connections. connect to the digital ground plane. pins: 2, 17, 34, 55, 64, 74, 85, 96, 106, 115, 124, 132, 138, 145, 152, 159, 168 see list v dd33 pad ring digital power connections. connect to the digital 3.3 volt power supply and decouple to the digital ground plane. pins: 1, 33, 63, 73, 84, 95, 105, 114, 123, 137, 144, 151, 167 see list v dd25 core logic digital power connections. connect to the digital 2.5 volt power supply and decouple to the digital ground plane. pins: 16, 54, 107, 158 43 av ss ground connection for the clock pll circuits. connect to the digital ground plane 42 av dd analog power connections for the clock pll circuit. connect to a separately decoupled 2.5 volt power supply and decouple directly to the av ss pin.. control signals 49 resetb reset. when this input is set low it will reset all the internal registers to the default states. refer to the section on the control registers for details of these states. the device must be reset after it is powered-up. 53 oe when this pin is set high the outputs of the FLI2200 will be enabled; when it is set low the outputs will be set into a high-impedance state. 56-58 iformat 2-0 input signal format control. the settings of these pins set the format of the input signal. this can be overridden by the ifmtovr bit, bit 3 in register 00 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 00 h for details. 59-61 oformat 2-0 output signal format control. the settings of these pins set the format of the output signal. this can be overridden by the ofmtovr bit, bit 3 in register 07 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 07 h for details. 44-45 daddr 1-0 the settings of daddr 1-0 allow the device address of the control bus to be programmed to prevent conflict with the other devices connected to the bus. daddr 1-0 allow the device address to be set to any of the following values: c0/c1 h , c2/c3 h , e0/e1 h , e2/e3 h . please refer to the section ?control bus operation and protocol? for further information. 46 mode when this pin is set low the control bus will operate in the slave mode; allowing the device to programmed from an external controller. when it is set high the FLI2200 will self-program from an external i 2 c memory connected to the bus. please refer to the ?control bus operation and control protocol? section for more details. 47 sda 2-wire serial control bus data. data can be written to the control registers via this pin when it is in the input mode and data can be read from the status registers when it is in the output mode. refer to the section on the serial port for timing and format details and to the section on the registers for programming information. 48 scl 2-wire serial control bus clock. when the control port operates in slave mode this pin will be an input and when it operates in the self programming mode it will be an output. 40 pixclk pixel clock input. this clock is used to drive all the circuits in the FLI2200. an internal pll is used to upconvert this clock to provide the master clock signal and other clocks used internally. note that when the FLI2200 is used in the d1 input mode the pixclk input should run at the rate of two cycles per pixel (one for luma and one for chroma). 62 n/p/in/out ntsc/pal input or output. the default function of this pin is ntsc/pal signal indicator output. when the input video signal is a 525 line signal this pin will be set high and when it is a 625 line signal the pin is set low. this function of this pin can be programmed to be an input according to the setting of this pin if the npop 1-0 bits, bits 5-4 in register 03 h , are set to 00 h , overriding the internal line counter. i.e., it will treat the signal as a 525 line signal when it is set high and a 625 line signal when it is set low.
FLI2200 rev. 1.04, 1/19/01 6 company confidential ? 2000-2001 faroudja labs, inc. pin # name description control signals (contd.) 52 nomem no memory mode control input. this pin controls the operation of the FLI2200 as follows: when this pin is set low the device is used with external field memories and operates in the full set of deinterlacing modes, i.e., motion adaptive video deinterlacing and full frame film source deinterlacing using 3:2 pulldown detection (2:2 pulldown for 625/50 sources). when this pin is set high the FLI2200 is forced into the intra-field only deinterlacing mode, which requires no external memories, allowing the FLI2200 to be used in low-cost applications where the ultimate video quality is not a requirement. to ensure proper startup of the sdrams this pin should be set high during the power-up sequence. this can be overridden by the nmovr bit, bit 1 in register 05 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 05 h for details. input signals 27-18 g/yin 9-0 10-bit green or luminance signal input bus. the mode is set by the iformat 2-0 pins. this can be overridden by the ifmtovr bit, bit 3 in register 00 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 00 h for details. this signal is sampled on the rising edge of pixclk. 15-6 b/cbin 9-0 10-bit blue or cb chroma signal input bus. the mode is set by the iformat 2-0 pins. this can be overridden by the ifmtovr bit, bit 3 in register 00 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 00 h for details. bits 6, 4 and 3 in register 08 h specify the busses used in the multiplexed modes. in all cases the signals are sampled on the rising edges of pixclk. in the y cb cr and y pb pr modes the cb or pb signal is sampled on alternate rising edges of pixclk in 4:2:2 mode. the frequency of pixclk will be 27 mhz in the multiplexed y/cb/cr mode and 13.5 mhz in all other modes. these pins should be tied low when not used. 39-35 r/crin 9-0 10-bit red or cr chroma signal input bus. the mode is set by the iformat 2-0 pins. 32-28 this can be overridden by the ifmtovr bit, bit 3 in register 00 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 00 h for details. bits 6, 4 and 3 in register 08 h specify the busses used in the multiplexed modes. in all cases the signals are sampled on the rising edges of pixclk. in the y cb cr mode the cr signal is sampled on alternate rising edges of pixclk in 4:2:2 mode. the frequency of pixclk will be 27 mhz in the multiplexed y/cb/cr mode and 13.5 mhz in all other modes. these pins should be tied low when not used. 3 hsyncrefi horizontal sync or reference. the horizontal sync or reference of the input signal should be connected to this pin. the function is programmed with bit 4 in register 00 h . the polarity and position of the sync or reference pulse relative to the start of active video are both programmable within a small range. when the FLI2200 is used in the itu-r bt 601/d1 input mode with embedded syncs (iformat = 110) this input is not used and should be tied low; in this case all sync information will be derived from the signal. 4 vsyncrefi v ertical sync or reference. the vertical sync or reference of the input signal should be connected to this pin. the function is programmed with bit 4 in register 00 h . the polarity and position of the sync or reference pulse relative to the start of active video are both programmable within a small range. when the FLI2200 is used in the itu-r bt 601/d1 input mode with embedded syncs (iformat = 110) this input is not used and should be tied low; in this case all sync information will be derived from the signal. 5 fldin field identifier input. the field identifier output of the source signal should be connected to this pin. a low setting signifies an even field and a high level signifies an odd field. when bit 4 in register 00 h is set low, the input timing is based on href and vref and this signal is required. when this bit is set high the input timing is based on hsync and vsync and this signal is generated internally and is not required. when bit 5 in register 06 is set high this signal is also used as the frame boundary identifier for 30 hz film sources.
? 2000-2001 faroudja labs, inc. company confidential 7 rev. 1.04, 1/19/01 FLI2200 pin # name description output signals 65-72 g/yout 9-0 green or luminance output bus. in the rgb mode this output is the green signal and in the 75-76 ycbcr mode it is the y signal. the mode is set by the oformat 2-0 pins. this can be overridden by the ofmtovr bit, bit 3 in register 07 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 07 h for details. the signal is clocked out on the falling edge of yclko. 93-94 b/cbout 9-0 blue or cb chrominance output bus. in the rgb mode this output is the blue signal, in the 97-104 y cb cr mode it is the cb signal. the mode is set by the oformat 2-0 pins. this can be overridden by the ofmtovr bit, bit 3 in register 07 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 07 h for details. the busses used in the multiplexed modes are set by means of bit 5 in register 08 h . the signal is clocked out on the falling edge of yclko in the rgb and yuv 4:4:4 modes, on the falling edge of yclko prior to the next rising edge of cclko in the yuv 4:2:2 mode, and on the rising edge of memclko in the multiplexed ycbcr (pseudo d1) mode. 77-83 r/crout 9-0 red or cr chrominance output bus. in the rgb mode this output is the red signal, in the 86-88 ycbcr mode it is the cr signal. the mode is set by the oformat 2-0 pins. this can be overridden by the ofmtovr bit, bit 3 in register 07 h , allowing this function to be set or changed via the i 2 c bus. please refer to the description of register 07 h for details. the busses used in the multiplexed modes are set by means of bit 5 in register 08 h . the signal is clocked out on the falling edge of yclko in the rgb and yuv 4:4:4 modes, on the falling edge of yclko prior to the next rising edge of cclko in the yuv 4:2:2 mode, and on the rising edge of memclko in the multiplexed ycbcr (pseudo d1) mode. 116 cclko chroma output sampling clock. this clock is derived from pixclk and will be at half the frequency of yclko. in 30-bit 4:2:2 output mode the chroma output signals will change on the falling edge of yclko prior to the next rising edge this clock. 117 yclko luma output sampling clock. this clock is derived from pixclk and is double the frequency of pixclk. in 30-bit and 20-bit output modes the output signals will change on the falling edge of this clock. 89 vrefo start of active field or frame indicator. this signal goes high to indicate the first active line in each field or frame and goes low during the vertical blanking interval. the polarity and timing of this signal are programmable. 90 hrefo start of active line indicator output. this signal goes high to indicate the first active pixel in each line and goes low during the horizontal blanking interval. the polarity and timing of this signal are programmable. 91 vsync/ vertical sync output. this signal provides the vertical sync function for the outputs. its crefo polarity is programmable to be active high or active low. it can also be programmed to be a composite reference for applications requiring this instead of sync. 92 h/csynco horizontal or composite sync output. this signal provides the horizontal sync function for the outputs. its polarity is programmable to be active high or active low. this signal can also be programmed to be the composite sync output, csync. 110 film film mode detector output. this pin will be set high when the FLI2200 detects that the video input was converted from 24 fps film with a telecin machine. if film mode is not detected this pin will be set low.
FLI2200 rev. 1.04, 1/19/01 8 company confidential ? 2000-2001 faroudja labs, inc. pin # name description sdram interface signals 125-131 addr 10-0 sdram address bus. this signal bus is used to address the external sdram(s) used for 133-136 field memories. it should be connected to the a 10-0 bus of the memory chip(s). please refer to the applications section of this data sheet for further details. 176-169 data 29-0 sdram data bus. this signal bus is used to transfer the data to and from the external 166-160 sdram(s) used for field memories. it should be connected to the dq 29-0 bus of the memory 157-153 chip when using a 64 mbit sdram. when using two 16 mbit sdrams this 30-bit bus may 150-146 be connected to the two 16-bit data busses of the memories in two ways: either connect 16 143-139 lines to one chip and 14 to the other, or connect 15 to both. in all cases the two unused data lines on the memory chip(s) should be connected to ground via 22 k resistors. please refer to the applications section of this data sheet for further details. 118 memclko sdram clock and 2x output sampling clock. this clock is derived from pixclk and will be at double the frequency of yclko. this active signal should be connected to the clk pin(s) on the sdram(s). when the 10-bit output mode selected the output signals will also change at this clock rate and this should then be used as the output clock.. 119 wen sdram write enable. this active low signal should be connected to the we pin(s) on the sdram(s). 120 rasn sdram row address select. this active low signal should be connected to the ras pin(s) on the sdram(s). 121 casn sdram column address select. this active low signal should be connected to the cas pin(s) on the sdram(s). 122 bsel sdram bank select. when using two 16 mbit sdrams this signal should be connected to the ba (also called bs or a 11 ) pin on both sdrams. when using a 64 mbit sdram this signal should be connected to the ba0 (also called bs0 or a 11 ) pin on the sdram and ba1/ bs1 (also called ba when ba0 is referred to as a 11 ) should be tied low. test inputs 41, 50, test 5-0 these pins are used for test purposes only and should always be tied low for normal operation. 51, 108, 109, 111 test outputs 112, 113 testo 1-0 these pins are test outputs and should be left unconnected in normal operation.
? 2000-2001 faroudja labs, inc. company confidential 9 rev. 1.04, 1/19/01 FLI2200 description of functional blocks note on signal conventions used in this document: the following conventions are used to denote the three component signal formats used in the FLI2200: the name cb is used to denote the b-y component, regardless of the actual color space (cb, pb, etc.). the name cr is used to denote the r-y component, regardless of the actual color space (cr, pr, etc.). y cb cr denotes a 3-bus signal, i.e., 3 x 10 bits, with the three components unmultiplexed. signals in this format can have either 4:4:4 or 4:2:2 sampling structures. rgb signals will also be in this format, with a 4:4:4 sampling structure. y cb/cr denotes a 2-bus signal, i.e., 2 x 10 bits, with the cb and cr components multiplexed. signals in this format will always have a 4:2:2 sampling structure. y/cb/cr denotes a 1-bus signal, i.e., 1 x 10 bits, with all three components multiplexed. signals in this format will always have a 4:2:2 sampling structure. at the input this signal will be in parallel d1 format with either embedded timing codes or external horizontal and vertical timing references. system clock generation block a number of system clocks are derived from the pixclk input using frequency multiplier circuits. this eliminates the need for an external high frequency clock driver and permits the device to be driven directly by the pixel clock of the input signal. control interface and register block the control interface and register block consists of a 2-wire serial bus controller and a number of control and status registers. when a write-byte command is received on the bus the controller writes bytes of data received from the bus into the control registers . when a read-byte command is received on the bus the decoder reads information bytes from the status registers and outputs them on the bus. the bus is generally i 2 c compatible. input formatter block the input formatter block consists of two sections, the color space converter and the multiplexer/demultiplexer. the FLI2200 processes all signals in 4:2:2 y cb/cr format. in order to allow the device to be operated with rgb inputs an optional color space conversion matrix is incorporated. after conversion the chroma components will be decimated to provide the 4:2:2 format. the FLI2200 can also be used with component inputs. the signals can be in 3 x 10-bit y cb cr format, 2 x 10-bit y cb/cr format or 1 x 10-bit y/cb/cr (d1) format. regardless of which format is used the signals will all be converted into 2 x 10-bit y cb/cr format in this block before further processing. thus, if the input format selected is 3 x 10-bit y cb cr (or rgb) the chroma signals will be multiplexed, with an optional decimation stage for 4:4:4 inputs. conversely, if the input mode selected is 1 x 10-bit y/cb/cr at 27 mhz the luma and chroma signals will be demultiplexed. 2 x 10 bit y cb/cr signals will not require any processing in this block. at the input, a programmable gain function can be used to maximize the signal range if the input signal has sync on y or g. after the sync is stripped from the signal the gain function expands r g b or y cb cr to the full 10-bit dynamic range to minimize quantization effects in the processing. the y and cb cr signal gains can also be programmed independently. when the d1 mode is selected the embedded codes will be detected to generate all timing information, eliminating the need to use external syncs in this mode. the gains will be set automatically in this case. luma processing block the luma processing block consists of a motion detector, film mode detector with bad-edit detector, the interpolator and luma line doubling fifos. the motion detector is frame based and compares the luma value of the current pixel and the same pixel in the previous frame. this is done in both the odd and even fields to generate a motion vector which is then used to switch the signal processing between field interleave and spatial interpolation modes on a pixel by pixel basis. in this way, non-moving parts of the picture, where sharpness is readily detected by the viewer, will not be interpolated and will have maximum sharpness. conversely, moving parts of the picture, where sharpness is not easily detected by the viewer, will be interpolated to avoid motion artifacts. the consequences of interleaving fields in areas of the picture containing motion are significantly worse than the loss of resolution caused by interpolation. the film mode detector detects the 3:2 or 2:2 pulldown sequences from telecin conversion. converting 24 frame/sec. film to 60 field/sec. maps two film frames ( 1 / 12 sec.) into five video fields (also 1 / 12 sec.), alternating between three odd and two even fields and three even and two odd fields. this pattern repeats over ten video fields. for further information on film mode please refer to the applications section of this data sheet. converting 24 frame/sec. film to 50 field/sec. video is done by running the film at 25 frames/sec. this is the same procedure as converting 30 frame/sec. film to 60 field/sec. video and results in the much simpler pattern of one film frame being mapped into one odd and one even field of video. in all cases, the film mode detector detects these sequences in the signal and uses them to correctly pair odd and even fields originating from the same film frame. once this is done, these field pairs can be interleaved without consideration of motion since there is, by definition, no motion between them. film mode overrides video mode processing.
FLI2200 rev. 1.04, 1/19/01 10 company confidential ? 2000-2001 faroudja labs, inc. the bad edit detector continually monitors the sequences for breaks caused by video edits made after the telecin transfer. there are 25 possible ways for the 3:2 pulldown sequence to be interrupted, and only two of these will not result in a break in the sequence. the bad edit detector looks for the break and forces the FLI2200 to switch out of film mode and into video mode before the bad edit is seen on the screen. the film mode detector will then reaquire the pulldown sequence, allowing the system to be switched back into film mode transparently. note that film mode detection is not done in the peripheral areas of the frame; this prevents the bad edit detector from causing the system to drop out of film mode in the presence of on-screen display (osd) graphics, such as subtitles, added to the video in these regions by the source, e.g., a dvd player. however, any graphics added to the central zone can cause the system to drop out of film mode any time they change, since the changes will generally not be synchronized to the 3:2 pulldown sequence, in which case they will be indistinguishable from bad edits. the intra-field interpolator is used to generate the missing pixels in the field when motion is detected in video mode and the pixels from the previous field cannot be interleaved. the FLI2200 uses a new diagonal interpolation algorithm, directional correlation deinterlacing?, (dcdi?, patent pending) that computes and tracks the angles of edges and uses this information to optimally fill in the missing pixels. conventional vertical interpolation algorithms work well on edges close to the horizontal and vertical directions but can completely break down as the angles of edges become more diagonal. diagonal interpolation eliminates this problem. the operation of the FLI2200 can be forced into the intra-field diagonal interpolation mode at all times, allowing it to be used without external field memories in low-cost applications. finally, the results of the motion detector, film mode detector and bad edit detector are used to control the signal paths into the de-interleaving fifos, determining whether interpolated pixels or pixels from the previous field are used in the interleaving process. chroma processing block the chroma processing block consists of a cross-color suppressor, chroma line-averager and the chroma line doubling fifos. positioning the cross-color suppressor in the deinterlacer takes advantage of the frame buffers already required for temporal processing and eliminates the need to use a 3-d comb filter with duplicate frame buffers. the cross-color suppressor helps to eliminate residual cross-color after the decoder. with the exception of 3-d decoders, all decoders, such as the faroudja fli2000, use a 2-d comb filter and/or notch filter, which leave residual cross-color under certain circumstances, such as diagonal edges, and the frame-based cross-color suppressor eliminates this in most cases, leaving the residual cross- color at a very low level. complete suppression is only possible in the absence of motion because some conditions (diagonal edges moving diagonally at rates with certain relationships to the field rate) result in signals which are completely impossible to fully separate because the luma and chroma spectra are completely superimposed. the chroma line averager is used to perform interpolation in the chroma path and passes the deinterlaced chroma signals into the line doubler memories. field memory interface block the field memory interface block formats the data and generates all the addressing required to use standard sdram for the field memories. the FLI2200 requires memory in a 1 mbit x 30 configuration. this can be achieved either by using two 16 mbit (1 mbit x 16) sdrams or one 64 mbit (2 mbit x 32) sdrams. the FLI2200 was designed to operate with the micron mt48lc1m16a1 and mt48lc2m32b2; it is also compatible with the following devices: vendor 16 mbit 64 mbit fujitsu mb81f161622c mb81f643242b hyundai hy57v161610 hy57v653220 micron mt48lc1m16a1 mt48lc2m32b2 samsung k4s161622d k4s643232c the FLI2200 is also compatible with 1m x 32 sgrams. in all cases the speed grade required is application dependent, the sdram interface operates at twice the input pixel rate. for ntsc/pal inputs (13.5 mpix/sec.) the sdram clock speed requirement is 54 mhz, so that the lowest speed grade devices (10 nsec./100 mhz) will easily meet these requirements. output formatter block the output formatter block consists of two sections, the multiplexer/demultiplexer and the color space converter. the multiplexer/demultiplexer allows the signal format to be converted from the 4:2:2 y cb/cr format used internally to either y cb cr or y/cb/cr. an optional interpolation filter then allows the signals to be converted to 4:4:4 format when the y cb cr mode is selected. the color space converter further allows the y cb cr 4:4:4 signals to be converted into r g b 4:4:4 format. the 4:2:2 y cb cr signal can also be converted into y pb pr.
? 2000-2001 faroudja labs, inc. company confidential 11 rev. 1.04, 1/19/01 FLI2200 memory map register bits default addr. name 76543210v alue 00 h input cclmpen yclmpen sonyg sync/ref ifmtovr iformat 2-0 d0 h 01 h yclamp yclamp 7-0 40 h 02 h cclamp cclamp 7-0 00 h 03 h np x npstat npop 1-0 cclamp 9-8 yclamp 9-8 18 h 04 h delay cdelay 3-0 cswapi ydelay 2-0 b4 h 05 h mode1 fm2430 x test test dcdion filmon nmovr nomem 0c h /8c h 06 h mode2 csync vitsen f30hz f30inv force30 motion 1-0 pcomp 05 h 07 h output cswapo chrphs cintdis oblnken ofmtovr oformat 2-0 10 h 08 h iosel d1valid cinsel coutsel d1insel 1-0 fsyncdel 2-0 52 h 09 h gain xxxxxx yingain cingain 03 h 0a h fdelay bsstart 7-0 4a h 10 h hsstn hsstartn 7-0 00 h 11 h hsspn hsstopn 7-0 00 h 12 h hrstn hrstartn 7-0 00 h 13 h hrspn hrstopn 7-0 00 h 14 h vmsn vsstartn 5-4 vsstopn 5-4 vrstartn 5-4 vrstopn 5-4 00 h 15 h vsssn vsstartn 3-0 vsstopn 3-0 00 h 16 h vrssn vrstartn 3-0 vrstopn 3-0 00 h 17 h vbimsn x vbstartn 4 x vbstopn 4 vbistartn 5-4 vbistopn 5-4 00 h 18 h vbtn vbstartn 3-0 vbstopn 3-0 00 h 19 h vbitn vbistartn 3-0 vbistopn 3-0 00 h 20 h hsstp hsstartp 7-0 00 h 21 h hsspp hsstopp 7-0 00 h 22 h hrstp hrstartp 7-0 00 h 23 h hrspp hsrtopp 7-0 00 h 24 h hmsp hsstartp 9-8 hsstopp 9-8 hrstartp 9-8 hrstopp 9-8 00 h 25 h vsstp vsstartp 7-0 00 h 26 h vsspp vsstopp 7-0 00 h 27 h vrstp vrstartp 7-0 01 h 28 h vrspp vrstopp 7-0 01 h 29 h vbstp vbstartp 7-0 01 h 2a vbspp vbstopp 7-0 00 h 2b vbistp vbistartp 7-0 02 h 2c vbispp vbistopp 7-0 08 h 2e h vbtp te s t x x usehsize x hsize 10-8 03 h 2f h hsize hsize 7-0 60 h 30 h inv1 isyncinv orefinv osyncinv datblnk hdatblnk test test ccson 05 h 31 h edbl edblnkl 7-0 e0 h
FLI2200 rev. 1.04, 1/19/01 12 company confidential ? 2000-2001 faroudja labs, inc. 32 h edbr edblnkr 7-0 52 h 33 h edbt edblnkt 7-0 42 h 34 h edbbn edblnkbn 7-0 f4 h 35 h edbbp edblnkbp 7-0 58 h 36 h edbms edblnkl 8 edblnkr 9-8 edblnkt 8 edblnkbn 9-8 edblnkbp 9-8 66 h 37 h fmbl fmblnkl 7-0 96 h 38 h fmbr fmblnkr 7-0 58 h 39 h fmbt fmblnkt 7-0 42 h 3a h fmbbn fmblnkbn 7-0 f4 h 3b h fmbbp fmblnkbp 7-0 58 h 3c h fmbms fmblnkl 8 fmblnkr 9-8 fmblnkt 8 fmblnkbn 9-8 fmblnkbp 9-8 66 h 3d h test test 7-0 14 h 3e h test test 7-0 0e h 3f h test test 7-0 60 h 40 h test test 7-0 05 h 41 h test xxxx test 3-0 0c h 42 h test test 7-0 14 h through see register descriptions for default values of these registers 4c h test test 7-0 38 h 4d h test x x x test 4-0 00 h 4e h pfilmxxxx test 3-0 07 h 4f h pfthr test 7-0 04 h 50 h test x x test 5-0 14 h 51 h test test 7-0 18 h 52 h test test 7-0 06 h 53 h test test 7-0 30 h 54 h test test 7-0 30 h 60 h pll0 pll mdiv 7-0 18 h 61 h pll1 pll ndiv 7-0 30 h 62 h pll2 lock x disable pbyp pllovr pdiv 2-0 02 h /82 h 63 h odis x routdis goutdis boutdis 00 h 64 h inv2 te s t 1-0 invyclk test 4-0 00 h 65 h test test 7-0 00 h 66 h sdel x x x sdel 4-0 00 h 67 h test test 7-0 08 h 71 h test test 7-0 00 h 72 h test xxxxx test 2-0 00 h 7e h idl chipid 7-0 41 h 7f h idh chipid 15-8 4b h register bits default addr. name 76543210v alue
? 2000-2001 faroudja labs, inc. company confidential 13 rev. 1.04, 1/19/01 FLI2200 register details note: all values are binary except for those with an h suffix, which are hexadecimal. * indicates default value address 00 h : input control register . default value d0 h the eight bits in the input register control the front-end configuration, as shown below: bit 76543 210 mnemonic cclmpen yclmpen sonyg sync/ref ifmtovr iformat 2 iformat 1 iformat 0 default value 1 1 0 1 0 0 0 0 cclmpen : the cclmpen bit is used to enable the chroma clamp circuit, as follows: 0 = chroma clamp disabled. the input clamp levels will be used 1* = chroma clamp enabled. the clamp levels will be set according to the value of the cclamp data in register 02 h . yclmpen : the yclmpen bit is used to enable the luma clamp circuit, as follows: 0 = luma clamp disabled. the input clamp level will be used 1* = luma clamp enabled. the clamp level will be set according to the value of the yclamp data in register 01 h . sonyg : the sonyg bit is used according to whether or not there is sync on the luma/green input, as follows: 0* = no sync pulses on the luma/green channel input. 1 = luma/green channel input contains sync pulses. when this bit is set high the y and cb cr signals will be expanded to full scale after sync removal to maximize the dynamic range of the processing operations, overriding the settings of the yingain and cingain bits in register 09 h . when this bit is set low the gains can be set independently with the yingain and cingain bits in register 09 h . sync/ref : the sync/ref bit is used to define the input timing signals, as follows: 0 = the FLI2200 is configured to use horizontal and vertical references as timing signals. 1* = the FLI2200 is configured to use horizontal and vertical sync pulses as timing signals. ifmtovr : the ifmtovr bit is used to control the input format function, as follows: 0* = the FLI2200 is configured to use the input format defined by the iformat 2-0 pins, pins 56-58. the formats defined will be same as those defined for the iformat 2-0 bits. 1 = the FLI2200 is configured to use the input format defined by the iformat 2-0 bits in this register, overriding the pin settings. iformat 2-0 : the iformat 2-0 bits are used to define the format of the input signals, as follows: iformat 2-0 input signal format 000* = y cb/cr 001 = y cr cb 010 = y pb/pr 011 = y pr pb 10x = r g b 110 = y/cb/cr (d1, with embedded timing) 111 = y/cb/cr (d1, with external/separate syncs) set the invyclk bit, bit 5 in register 62 h , high when using the d1 input modes, 11x. the busses used for the multiplexed signals (cb/cr and y/cb/cr) in modes 000 and 11x are determined by the settings of the cinsel and d1insel bits in register 08 h , as shown on page 49.
FLI2200 rev. 1.04, 1/19/01 14 company confidential ? 2000-2001 faroudja labs, inc. address 01 h : yclamp control register. default value 40 h the eight bits in the yclamp register set the luma clamp level, as shown below: bit 76543 210 mnemonic yclamp 7 yclamp 6 yclamp 5 yclamp 4 yclamp 3 yclamp 2 yclamp 1 yclamp 0 default value 0 4 0 0 0 0 0 0 yclamp 7-0 these bits, in conjunction with bits 1-0 in register 03 h , set the clamp level for the luma signal when the yclmpen bit is set high, as follows: 000 h * = minimum clamp level 000 h (0). 040 h * = default clamp level 040 h (64). 3ff h = maximum clamp level, 3ff h (1023) address 02 h : cclamp control register. default value 00 h the eight bits in the cclamp register set the luma clamp level, as shown below: bit 76543 210 mnemonic cclamp 7 cclamp 6 cclamp 5 cclamp 4 cclamp 3 cclamp 2 cclamp 1 cclamp 0 default value 0 0 0 0 0 0 0 0 cclamp 7-0 these bits, in conjunction with bits 3-2 in register 03 h , set the clamp level for the chroma signals when the cclmpen bit is set high, as follows: 000 h * = minimum clamp level 000 h (0). 200 h * = default clamp level 200 h (512). 3ff h = maximum clamp level, 3ff h (1023)
? 2000-2001 faroudja labs, inc. company confidential 15 rev. 1.04, 1/19/01 FLI2200 address 03 h : np (n tsc /p al ) control register. default value 18 h seven bits in the np register are used to control the ntsc/pal operation and the clamp levels, as shown below. bit 6 is read only.: bit 76543 210 mnemonic x npstat npop 1 npop 0 cclamp 9 cclamp 8 yclamp 9 yclamp 8 default value x r/o 0 1 1 0 0 0 x: this bit is not used and does not exist physically. npstat: this bit indicates the status of the ntsc/pal (525/625 line) detector. it is a read-only (r/o) function. this bit, as well as the np/in/out pin when it is an output, will indicate the actual line count, regardless of the settings of the npovr 1-0 bits in this register, as follows: 0 = 625 line signal detected. 1 = 525 line signal detected. npop 1-0 : these bits configure the operation of the FLI2200 and the n/p/in/out pin, pin 62, as follows: npop 1-0 configuration n/p/in/out function 00 = set ntsc/pal mode according to setting of n/p/in/out pin. i nput 01* = auto detect signal using internal ntsc/pal detector. output 10 = force FLI2200 to ntsc operation. output (high) 11 = force FLI2200 to pal operation. output (low) cclamp 9-8 : these bits, in conjunction with bits 7-0 in register 02 h , set the clamp level for the chroma signals. these are the most significant bits of the 10-bit value. see description of register 02 h for details. yclamp 9-8 : these bits, in conjunction with bits 7-0 in register 01 h , set the clamp level for the luma signal. these are the most significant bits of the 10-bit value. see description of register 01 h for details. address 04 h : delay control register. default value b4 h the seven bits in the delay register set the luma and chroma delay at the front end, as shown below: bit 76543 210 mnemonic cdelay 3 cdelay 2 cdelay 1 cdelay 0 cswapi ydelay 2 ydelay 1 ydelay 0 default value 1 0 1 1 0 1 0 0 cdelay 3-0 : these bits set the delay for the chroma signals, as follows: 0 h = minimum chroma delay, 0 pixels. b h * = default chroma delay, 11 pixels. f h = maximum chroma delay, 15 pixels. cswapi: this bit swaps the cb and cr components at the input, as follows: 0* = chroma components not swapped (normal). 1 = chroma components swapped (reversed). ydelay 3-0 : these bits set the delay for the luma signal, as follows: 0 h = minimum luma delay, 0 pixels. 4 h * = default luma delay, 4 pixels. 7 h = maximum luma delay, 7 pixels.
FLI2200 rev. 1.04, 1/19/01 16 company confidential ? 2000-2001 faroudja labs, inc. address 05 h : mode1 control register. default value 0c h the six bits in the mode1 register control various deinterlacing functions, as shown below: bit 76543 210 mnemonic fm2430 x test test dcdion filmon nmovr nomem default value r/o x 0 0 1 1 0 0 fm2430: this read-only bit indicates the type of film mode detected, as follows: 0 = 2:2 pulldown detected. this is the normal mode when the video source is 625 line pal. note that 2:2 pulldown in ntsc indicates a 30 fps film source. this mode will only be active if the f30hz bit in register 06 h is set high. 1 = 3:2 pulldown detected. this indicates 24 fps film in ntsc. this mode is not active when the video source is 625 line pal. x: this bits is not used and does not physically exist. test: these bits turn on special test functions, as follows: 0* = normal mode. 1 = test mode, not for normal use. dcdion: this bit controls the operation of the interpolator, as follows: 0 = dcdi off. vertical interpolation is used. 1* = dcdi on. diagonal correlation interpolation is used. filmon: this bit controls the operation of the film mode detector, as follows: 0 = film mode detector is disabled, all signals processed as video. 1* = film mode detector is enabled, film and video sourced signals are processed separately. nmovr: this bit controls the operation of the FLI2200, as follows: 0* = operating mode is determined by the setting of the nomem pin, pin 52. 1 = operating mode is determined by the setting of the nomem bit, overriding the setting of the nomem pin, pin 52.. nomem: this bit controls the operation of the FLI2200, as follows: 0* = the FLI2200 is used with external field memories and operates in the full set of deinterlacing modes, i.e., motion adaptive video deinterlacing and full frame film source deinterlacing using 3:2 pulldown detection (2:2 pulldown for 625/50 sources). 1 = the FLI2200 is forced into the intra-field only deinterlacing mode, which requires no external memories, allowing the FLI2200 to be used in low-cost applications where the ultimate video quality is not a requirement.
? 2000-2001 faroudja labs, inc. company confidential 17 rev. 1.04, 1/19/01 FLI2200 address 06 h : mode2 control register. default value 05 h the eight bits in the mode2 register control various deinterlacing functions, as shown below: bit 76543 210 mnemonic csync vitsen f30hz f30inv force30 motion 1 motion 0 pcomp default value 0 0 0 0 0 1 0 1 csync: this bit controls the output syncs, as follows, as follows: 0* = horizontal sync appears on the h/csynco output and vertical sync on the vsync/crefo output. 1 = composite sync appears on the h/csynco output and composite reference on the vsync/crefo output. vitsen: this bit controls the use of the film mode flag which sometimes appears on line 22, as follows: 0* = film mode flag is ignored and the internal film mode detector is operational. 1 = film mode flag is used to control film mode in the deinterlacer. f30hz: this bit controls the film mode detector when the signal comes from a 525 line (ntsc) source, as follows: 0* = disabled the detection of 30 fps film using 2:2 pulldown detection in 525 line ntsc. this prevents the accidental detection of this mode when the source is video, not 30 fps film. note that this does not disable 2:2 pulldown detection in 625 line pal. 1 = allow detection of 30 fps film using 2:2 pulldown detection in ntsc. f30inv: this bit controls the 30 fps film operation when the field flag input is used for frame detection (force30 = 1), as follows: 0* = fldin = 1 identifies first field in frame. 1 = fldin = 0 identifies first field in frame. force30: this bit controls the 30 fps film operation, as follows: 0* = 30 fps film mode operation controlled by internal film mode detector. 1 = 30 fps film mode operation controlled by fldin signal. motion 1-0 : these bits set the motion processing mode in the deinterlacer, as follows: motion 1-0 mode 0x test mode. 10* normal operation 11 test mode. pcomp: this bit controls the operation of the pal line averager, as follows: 0 = pal line averager will be operational when 625 line (pal) source signals are detected. 1* = pal line averager disabled. improved performance can be achieved with 625 line signals which have never been encoded into composite pal format and therefore do no require line averaging to eliminate hannover blinds.
FLI2200 rev. 1.04, 1/19/01 18 company confidential ? 2000-2001 faroudja labs, inc. address 07 h : output control register. default value 10 h the eight bits in the output register control the following output functions, as shown below: bit 76543 210 mnemonic c swap chrphs cintdis oblnken ofmtovr oformat 2 oformat 1 oformat 0 default value 0 0 0 1 0 0 0 0 cswap: this bit controls the sequence of the chroma outputs prior to demultiplexing at the output, as follows: 0* = normal mode, cb precedes cr in y cb/cr and y/cb/cr modes and cr and cb appear on the corresponding busses in y cr cb mode. 1 = inverted color mode. the cb and cr signals will be switched. r and b will also be swapped in the r g b mode. chrphs: this bit delays the chroma output in the y/cb/cr mode, as follows: 0* = normal mode, no delay 1 = chroma output is delayed by two luma pixels/one chroma pixel. cintdis: this bit controls the chroma interpolator, as follows: 0* = chroma interpolator enabled. this mode is only used to generate 4:4:4 y cr cb outputs. 1 = chroma interpolator disabled. this is the normal mode of operation and must be selected for all 4:2:2 output formats. note: selecting the 4:4:4 r g b output mode automatically enables the chroma interpolator. oblnken: this bit controls the output blanking, as follows: 0 = output blanking disabled. the output signal will be the same as the input in the blanking regions. 1* = output blanking enabled. the output signal will be blanked in the blanking regions regardless of the input signal. ofmtovr : the ofmtovr bit is used to control the output format function, as follows: 0* = the FLI2200 is configured to use the output format defined by the oformat 2-0 pins, pins 59-61. the formats defined will be same as those defined for the oformat 2-0 bits. 1 = the FLI2200 is configured to use the output format defined by the oformat 2-0 bits in this register, overriding the pin settings. oformat 2-0 : these bits are used to define the format of the output signals, as follows: oformat 2-0 output signal format 000* = r g b (4:4:4) 001 = y cr cb (4:2:2) 010 = y cb/cr + y/cb/cr (double rate d1, with external/separate syncs) 011 = y cb/cr + y/cb/cr (double rate d1, with embedded timing) 100 = y pb pr (4:2:2) 101 = y pb/pr 110 = y cb cr (4:4:4) 111 = test mode the busses used for the multiplexed signals (cb/cr and y/cb/cr) in modes 01x and 101 are determined by the settings of the coutsel bit in register 08 h , as shown on page 50.
? 2000-2001 faroudja labs, inc. company confidential 19 rev. 1.04, 1/19/01 FLI2200 address 08 h : iosel (iosel ect ) control register. default value 52 h the eight bits in the iosel register select the busses used for multiplexed signals, and set the film sync delay in the film mode detector, as shown below: bit 76543 210 mnemonic d1v alid cinsel coutsel d1insel 1 d1insel 0 fsyncdel 2 fsyncdel 1 fsyncdel 0 default value r/o 1 0 1 0 0 1 0 d1valid: this bit indicates the validity of the input in y/cb/cr (d1) mode. it is a read only function. this bit is set as follows: 0 = the FLI2200 has not been able to lock onto the input signal. 1 = the FLI2200 has locked onto the input signal. cinsel: this bit selects which bus is used for the multiplexed chroma input signal in the y cb/cr input mode, as follows: 0 = multiplexed chroma signal cb/cr is input on the b/cbin bus. 1* = multiplexed chroma signal cb/cr is input on the r/crin bus. coutsel: this bit selects which bus is used for the multiplexed chroma output signal in the y cb/cr output mode, as follows: 0* = multiplexed chroma signal cb/cr is output on the b/cbout bus. multiplexed pseudo-d1 signal y/cb/cr is output on the r/crout bus. 1 = multiplexed chroma signal cb/cr is output on the r/crout bus. multiplexed pseudo-d1 signal y/cb/cr is output on the b/cbout bus. d1insel 1-0 : these bits set the input bus used for the d1 (y/cb/cr) multiplexed input signal, as follows: d1insel 1-0 d1 bus 00 g/y 01 g/y 10* b/cb 11 r/cr fsyncdel 3-0 : these bits set the delay in the film mode detector, as follows: 0 h = minimum film sync delay, zero fields. 2 h * = default film sync delay, 2 fields. 4 h = maximum film sync delay, 4 fields. 5-7 h = not valid.
FLI2200 rev. 1.04, 1/19/01 20 company confidential ? 2000-2001 faroudja labs, inc. address 09 h : igain (i nput gain) control register. default value 03 h the two bits in the igain register set the gain of the input signals after sync removal, as shown below: bit 76543 210 mnemonic x x x x x x yingain cingain default value 0 0 0 0 0 0 1 1 yingain: this bit sets the gain of the luma input path, as follows: 0 = gain = 1. this value must be used when there is no sync on the input signal and the input signal has a full scale range. 1* = gain = 1.5625. this value can be used when there is sync on the input signal, allowing the signal to be stretched to full scale range after sync removal. cingain: this bit sets the gain of the luma input path, as follows: 0 = gain = 1. this value must be used when there is no sync on the luma input signal and the input signals have a full scale range. 1* = gain = 1.5625. this value can be used when there is sync on the luma input signal if the chroma signal range matches that of the luma signal. note that sonyg, bit 5 in register 00 h , overrides these bits when it is set low, forcing the gains to 1. address 0a h : bsstart (b lanking s ampling start) control register. default value 02 h the eight bits in the bsstart register set the start of the sampling period for the horizontal blanking level detector, as shown below: bit 76543 210 mnemonic bsstart 7 bsstart 6 bsstart 5 bsstart 4 bsstart 3 bsstart 2 bsstart 1 bsstart 0 default value 0 1 0 0 1 0 1 0 bsstartn 7-0 : these bits set the start of the 32-pixel sampling period for the blanking level detector. the adjustment is in 1 pixel increments relative to the start of the horizontal blanking interval, as follows: bsstartn 7-0 timing relative to start of blanking 00 h 0 pixels 4a h * 74 pixels ff h +127 pixels care should be taken to not allow the 32-pixel period extend beyond the end of the horizontal blanking interval.
? 2000-2001 faroudja labs, inc. company confidential 21 rev. 1.04, 1/19/01 FLI2200 address 10 h : hsstn (h orizontal s ync s tar t / n tsc ) control register. default value 00 h the eight bits in the hsstn register set the start of the output horizontal sync pulse when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic hsstartn 7 hsstartn 6 hsstartn 5 hsstartn 4 hsstartn 3 hsstartn 2 hsstartn 1 hsstartn 0 default value 00000 000 hsstartn 7-0 : these bits set the start of the output horizontal sync pulse when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hsstartn 7-0 timing relative to default value 80 h ?128 pixels 00 h * default timing 7f h +127 pixels address 11 h : hsspn (h orizontal s ync s to p / n tsc ) control register. default value 00 h the eight bits in the hsspn register set the end of the output horizontal sync pulse when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic hsstopn 7 hsstopn 6 hsstopn 5 hsstopn 4 hsstopn 3 hsstopn 2 hsstopn 1 hsstopn 0 default value 00000 000 hsstopn 7-0 : these bits set the end of the output horizontal sync pulse when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hsstopn 7-0 timing relative to default value 80 h ?128 pixels 00 h * default timing 7f h +127 pixels
FLI2200 rev. 1.04, 1/19/01 22 company confidential ? 2000-2001 faroudja labs, inc. address 12 h : hrstn (h orizontal r eference s tar t / n tsc ) control register. default value 00 h the eight bits in the hrstn register set the start of the output horizontal reference signal when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic hrstartn 7 hrstartn 6 hrstartn 5 hrstartn 4 hrstartn 3 hrstartn 2 hrstartn 1 hrstartn 0 default value00000 000 hrstartn 7-0 : these bits set the start of the output horizontal reference signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hrstartn 7-0 timing relative to default value 80 h ?128 pixels 00 h * default timing 7f h +127 pixels address 13 h : hrspn (h orizontal r eference s to p / n tsc ) control register. default value 00 h the eight bits in the hrspn register set the end of the output horizontal reference signal when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic hrstopn 7 hrstopn 6 hrstopn 5 hrstopn 4 hrstopn 3 hrstopn 2 hrstopn 1 hrstopn 0 default value00000 000 hrstopn 7-0 : these bits set the end of the output horizontal reference signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hrstopn 7-0 timing relative to default value 80 h ?128 pixels 00 h * default timing 7f h +127 pixels
? 2000-2001 faroudja labs, inc. company confidential 23 rev. 1.04, 1/19/01 FLI2200 address 14 h : vmsn (v ertical timing ms bits/ n tsc ) control register. default value 00 h the eight bits in the vmsn register are the most significant bits for the vertical sync and reference timing signals when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic vsstartn 5 vsstartn 4 vsstopn 5 vsstopn 4 vrstartn 5 vrstartn 4 vrstopn 5 vrstopn 4 default value 0 0 0 0 0 0 0 0 vsstartn 5-4 : these bits, in conjunction with bits 7-4 in register 15 h , set the start of the output vertical sync pulse when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 15 h for details. vsstopn 5-4 : these bits, in conjunction with bits 3-0 in register 15 h , set the end of the output vertical sync pulse when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 15 h for details. vrstartn 5-4 : these bits, in conjunction with bits 7-4 in register 16 h , set the start of the output vertical reference signal when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 16 h for details. vrstopn 5-4 : these bits, in conjunction with bits 3-0 in register 16 h , set the end of the output vertical reference signal when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 16 h for details. address 15 h : vstn (v ertical s ync t iming/ n tsc ) control register. default value 00 h the eight bits in the vstn register set the start and end of the output vertical sync pulse when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic vsstartn 3 vsstartn 2 vsstartn 1 vsstartn 0 vsstopn 3 vsstopn 2 vsstopn 1 vsstopn 0 default value 00000 000 vsstartn 3-0 : these bits, in conjunction with bits 7-6 in register 14 h , set the start of the output vertical sync pulse when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vsstartn 5-0 timing relative to default value 20 h ?32 lines 00 h * default timing 1f h +31 lines vsstopn 3-0 : these bits, in conjunction with bits 5-4 in register 14 h , set the end of the output vertical sync pulse when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vsstopn 5-0 timing relative to default value 20 h ?32 lines 00 h * default timing 1f h +31 lines
FLI2200 rev. 1.04, 1/19/01 24 company confidential ? 2000-2001 faroudja labs, inc. address 16 h : vrtn (v ertical r eference t iming/ n tsc ) control register. default value 00 h the eight bits in the vrtn register set the start and end of the output vertical reference signal when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic vrstartn 3 vrstartn 2 vrstartn 1 vrstartn 0 vrstopn 3 vrstopn 2 vrstopn 1 vrstopn 0 default value 0 0 0 0 0 0 0 0 vrstartn 3-0 : these bits, in conjunction with bits 7-6 in register 14 h , set the start of the output vertical reference signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vrstartn3-0 timing relative to default value 40 h ?32 lines 00 h * default timing 3f h +31 lines vrstopn 3-0 : these bits, in conjunction with bits 5-4 in register 14 h , set the end of the output vertical reference signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vrstopn 5-0 timing relative to default value 40 h ?32 lines 00 h * default timing 3f h +31 lines address 17 h : vbimsn (vbi timing ms bits/ n tsc ) control register. default value 00 h the six bits in the vbimsn register are the most significant bits for the vbi timing signals when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic x vbstartn 4 x vbstopn 4 vbistartn 5 vbistartn 4 vbistopn 5 vbistopn 4 default value x 0 x 0 0 0 0 0 vbstartn 4 : this bit, in conjunction with bits 7-4 in register 18 h , set the start of the output vertical blanking signal when the input signal comes from a 525 line (ntsc) source. this is the most significant bit of a 5-bit value. see description of register 18 h for details. vbstopn 4 : this bit, in conjunction with bits 3-0 in register 18 h , set the end of the output vertical blanking signal when the input signal comes from a 525 line (ntsc) source. this is the most significant bit of a 5-bit value. see description of register 18 h for details. vbistartn 5-4 : these bits, in conjunction with bits 7-4 in register 19 h , set the start of the output vbi data pass- through signal when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 19 h for details. vbistopn 5-4 : these bits, in conjunction with bits 3-0 in register 19 h , set the end of the output vbi data pass- through signal when the input signal comes from a 525 line (ntsc) source. these are the most significant bits of a 6-bit value. see description of register 19 h for details.
? 2000-2001 faroudja labs, inc. company confidential 25 rev. 1.04, 1/19/01 FLI2200 address 18 h : vbtn (v ertical b lanking t iming/ n tsc ) control register. default value 00 h the eight bits in the vbtn register set the start and end of the output vertical blanking signal when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic vbstartn 3 vbstartn 2 vbstartn 1 vbstartn 0 vbstopn 3 vbstopn 2 vbstopn 1 vbstopn 0 default value 0 0000 000 vbstartn 3-0 : these bits, in conjunction with bit 6 in register 17 h , set the start of the output vertical blanking signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstartn 4-0 timing relative to default value 10 h ?16 lines 00 h * default timing 0f h +15 lines vbstopn 3-0 : these bits, in conjunction with bit 4 in register 17 h , set the end of the output vertical blanking signal when the input signal comes from a 525 line (ntsc) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstopn 5-0 timing relative to default value 10 h ?16 lines 00 h * default timing 0f h +15 lines
FLI2200 rev. 1.04, 1/19/01 26 company confidential ? 2000-2001 faroudja labs, inc. address 19 h : vbitn (vbi data t iming/ n tsc ) control register. default value 28 h the eight bits in the vbtn register set the start and end of the output vbi data pass-through signal when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic vbistartn 3 vbistartn 2 vbistartn 1 vbistartn 0 vbistopn 3 vbistopn 2 vbistopn 1 vbistopn 0 default value 00101 000 vbistartn 3-0 : these bits, in conjunction with bits 3-2 in register 17 h , set the start of the output vbi data pass- through signal when the input signal comes from a 525 line (ntsc) source. this allows a selected contiguous group of lines during the vbi period to be unblanked to pass through the data on these lines. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbistartn 4-0 timing relative to default value 20 h ?32 lines 02 h * default timing 1f h +31 lines vbstopn 3-0 : these bits, in conjunction with bits 1-0 in register 17 h , set the end of the output vbi data pass- through signal when the input signal comes from a 525 line (ntsc) source. this allows a selected contiguous group of lines during the vbi period to be unblanked to pass through the data on these lines. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstopn 4-0 timing relative to default value 20 h ?32 lines 00 h * default timing 1f h +31 lines address 20 h : hsstp (h orizontal s ync s tar t / p al ) control register. default value 00 h the eight bits in the hsstp register set the start of the output horizontal sync pulse when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic hsstartp 7 hsstartp 6 hsstartp 5 hsstartp 4 hsstartp 3 hsstartp 2 hsstartp 1 hsstartp 0 default value 0 0000 000 hsstartp 7-0 : these bits, in conjunction with bits 7-6 in register 24 h , set the start of the output horizontal sync pulse when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hsstartp 9-0 timing relative to default value 200 h ?512 pixels 000 h * default timing 1ff h +511 pixels
? 2000-2001 faroudja labs, inc. company confidential 27 rev. 1.04, 1/19/01 FLI2200 address 21 h : hsspp (h orizontal s ync s to p / p al ) control register. default value 00 h the eight bits in the hsspp register set the end of the output horizontal sync pulse when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic hsstopp 7 hsstopp 6 hsstopp 5 hsstopp 4 hsstopp 3 hsstopp 2 hsstopp 1 hsstopp 0 default value 0 0 0 0 0 0 0 0 hsstopp 7-0 : these bits, in conjunction with bits 5-4 in register 24 h , set the end of the output horizontal sync pulse when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hsstopp 7-0 timing relative to default value 200 h ?512 pixels 000 h * default timing 1ff h +511 pixels address 22 h : hrstp (h orizontal r eference s tar t / p al ) control register. default value 00 h the eight bits in the hrstp register set the start of the output horizontal reference signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic hrstartp 7 hrstartp 6 hrstartp 5 hrstartp 4 hrstartp 3 hrstartp 2 hrstartp 1 hrstartp 0 default value 0 0 0 0 0 0 0 0 hrstartp 7-0 : these bits, in conjunction with bits 3-2 in register 24 h , set the start of the output horizontal reference signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hrstartp 7-0 timing relative to default value 200 h ?512 pixels 000 h * default timing 1ff h +511 pixels address 23 h : hrspp (h orizontal r eference s to p / p al ) control register. default value 00 h the eight bits in the hrspp register set the end of the output horizontal reference signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic hrstopp 7 hrstopp 6 hrstopp 5 hrstopp 4 hrstopp 3 hrstopp 2 hrstopp 1 hrstopp 0 default value 0 0 0 0 0 0 0 0 hrstopp 7-0 : these bits, in conjunction with bits 1-0 in register 24 h , set the end of the output horizontal reference signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: hrstopp 7-0 timing relative to default value 200 h ?512 pixels 000 h * default timing 1ff h +511 pixels
FLI2200 rev. 1.04, 1/19/01 28 company confidential ? 2000-2001 faroudja labs, inc. address 24 h : hmsp (h orizontal timing m s bits/ p al ) control register. default value 00 h the eight bits in the hmsp register are the most significant bits for the vertical sync and reference timing signals when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic hsstartp 9 hsstartp 8 hsstopp 9 hsstopp 8 hrstartp 9 hrstartp 8 hrstopp 9 hrstopp 8 default value 0 0 0 0 0 0 0 0 hsstartp 9-8 : these bits, in conjunction with bits 7-0 in register 20 h , set the start of the output vertical sync pulse when the input signal comes from a 625 line (pal) source. these are the most significant bits of a 10-bit value. see description of register 20 h for details. hsstopp 9-8 : these bits, in conjunction with bits 7-0 in register 21 h , set the end of the output vertical sync pulse when the input signal comes from a 625 line (pal) source. these are the most significant bits of a 10-bit value. see description of register 21 h for details. hrstartp 9-8 : these bits, in conjunction with bits 7-0 in register 22 h , set the start of the output vertical reference signal when the input signal comes from a 625 line (pal) source. these are the most significant bits of a 10-bit value. see description of register 22 h for details. hrstopp 9-8 : these bits, in conjunction with bits 7-0 in register 23 h , set the end of the output vertical reference signal when the input signal comes from a 625 line (pal) source. these are the most significant bits of a 10-bit value. see description of register 23 h for details. address 25 h : vsstp (v ertical s ync s tar t / p al ) control register. default value 00 h the eight bits in the vstp register set the start of the output vertical sync pulse when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vsstartp 7 vsstartp 6 vsstartp 5 vsstartp 4 vsstartp 3 vsstartp 2 vsstartp 1 vsstartp 0 default value 00000 000 vsstartp 7-0 : these bits set the start of the output vertical sync pulse when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vsstartp 7-0 timing relative to default value 80 h ?128 lines 00 h * default timing 7f h +127 lines
? 2000-2001 faroudja labs, inc. company confidential 29 rev. 1.04, 1/19/01 FLI2200 address 26 h : vsspp (v ertical s ync s to p / p al ) control register. default value 00 h the eight bits in the vsspp register set the end of the output vertical sync pulse when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vsstopp 7 vsstopp 6 vsstopp 5 vsstopp 4 vsstopp 3 vsstopp 2 vsstopp 1 vsstopp 0 default value 00000 000 vsstopp 7-0 : these bits set the end of the output vertical sync pulse when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vsstopp 7-0 timing relative to default value 80 h ?128 lines 00 h * default timing 7f h +127 lines address 27 h : vrstp (v ertical r eference s tar t / p al ) control register. default value 01 h the eight bits in the vrstp register set the start of the output vertical reference signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vrstartp 7 vrstartp 6 vrstartp 5 vrstartp 4 vrstopp 3 vrstopp 2 vrstopp 1 vrstopp 0 default value 00000 001 vrstartp 7-0 : these bits set the start of the output vertical reference signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vrstartp 7-0 timing relative to default value 80 h ?129 lines 01 h * default timing 7f h +126 lines address 28 h : vrspp (v ertical r eference s to p / p al ) control register. default value 01 h the eight bits in the vrspp register set the end of the output vertical reference signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vrstopp 7 vrstopp 6 vrstopp 5 vrstopp 4 vrstopp 3 vrstopp 2 vrstopp 1 vrstopp 0 default value 00000 001 vrstopp 7-0 : these bits set the end of the output vertical reference signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vrstopp 7-0 timing relative to default value 80 h ?129 lines 01 h * default timing 7f h +126 lines
FLI2200 rev. 1.04, 1/19/01 30 company confidential ? 2000-2001 faroudja labs, inc. address 29 h : vbstp (v ertical b lanking s tar t / p al ) control register. default value 01 h the eight bits in the vbstp register set the start of the output vertical blanking signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vbstartp 7 vbstartp 6 vbstartp 5 vbstartp 4 vbstartp 3 vbstartp 2 vbstartp 1 vbstartp 0 default value 0 0000 001 vbstartp 7-0 : these bits set the start of the output vertical blanking signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstartp 7-0 timing relative to default value 80 h ?129 lines 01 h * default timing 7f h +126 lines address 2a h : vbspp (v ertical b lanking s to p / p al ) control register. default value 00 h the eight bits in the vbstp register set the end of the output vertical blanking signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vbstopp 7 vbstopp 6 vbstopp 5 vbstopp 4 vbstopp 3 vbstopp 2 vbstopp 1 vbstopp 0 default value 0 0 0 0 0 0 0 0 vbstopp 7-0 : these bits set the end of the output vertical blanking signal when the input signal comes from a 625 line (pal) source. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstopp 7-0 timing relative to default value 80 h ?128 lines 00 h * default timing 7f h +127 lines
? 2000-2001 faroudja labs, inc. company confidential 31 rev. 1.04, 1/19/01 FLI2200 address 2b h : vbistp (vbi data s tar t / p al ) control register. default value 02 h the eight bits in the vbistp register set the start of the output vbi data pass-through signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vbistartp 7 vbistartp 6 vbistartp 5 vbistartp 4 vbistartp 3 vbistartp 2 vbistartp 1 vbistartp 0 default value 0 0000 010 vbistartp 7-0 : these bits set the start of the output vbi data pass-through signal when the input signal comes from a 625 line (pal) source. this allows a selected contiguous group of lines during the vbi period to be unblanked to pass through the data on these lines. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbistartp 7-0 timing relative to default value 80 h ?130 lines 02 h * default timing 7f h +125 lines address 2c h : vbispp (vbi data s to p / p al ) control register. default value 08 h the eight bits in the vbispp register set the end of the output vbi data pass-through signal when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic vbistartp 3 vbistartp 2 vbistartp 1 vbistartp 0 vbistopp 3 vbistopp 2 vbistopp 1 vbistopp 0 default value 0 0001 000 vbistopp 7-0 : these bits set the end of the output vbi data pass-through signal when the input signal comes from a 625 line (pal) source. this allows a selected contiguous group of lines during the vbi period to be unblanked to pass through the data on these lines. the number is a signed, two?s complement value. the adjustment is in 1 line increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: vbstopp 7-0 timing relative to default value 80 h ?136 lines 08 h * default timing 7f h +119 lines
FLI2200 rev. 1.04, 1/19/01 32 company confidential ? 2000-2001 faroudja labs, inc. address 2e h : hovr (h orizontal ov erride ) control register. default value 04 h the four bits in the hovr register control the horizontal line length, as shown below: bit 76543 210 mnemonic test x x hsizeovr x hsize 10 hsize 9 hsize 8 default value 0 x x 0 x 1 0 0 test: this bit is used to put the device into a special test mode, as follows: 0* = normal operating mode. 1 = test mode, not normally used. x: this bit is not used and does not exist physically. hsizeovr: this bit controls the horizontal line length, as follows: 0* = line length is set automatically set according to itu-r bt656 and the video standard, i.e., 858 pixels for 525 line (ntsc) signals and 864 pixels for 625 line (pal) signals. when the device is used with external memory for fully adaptive deinterlacing this bit must be set low, i.e., the nomem pin is tied low or the nmovr bit is set high and the nomem bit is set low. 1 = line length is set by the number of clock cycles in each horizontal period, as determined by the horizontal sync or reference input signal. in this mode the hsize register must be programmed to match this number for correct operation. this mode can only be used when the FLI2200 is configured in the stand-alone mode with no external memory (intra-field deinterlacing only), i.e., the nomem pin is tied high or the nmovr and nomem bits are set high. when the device is used with external memory for fully adaptive deinterlacing hsizeovr must be set low.. hsize 10-8 : these bits, in conjunction with bits 7-0 in register 2f h , set the total line length when the hsizeovr bit is set high . see description of register 2f h for details. address 2f h : hsize (h orizontal size) control register. default value 4c h the eight bits in the hsize register control the horizontal line length, as shown below: bit 76543 210 mnemonic hsize 7 hsize 6 hsize 5 hsize 4 hsize 3 hsize 2 hsize 1 hsize 0 default value 0 1 0 0 1 1 0 0 hsize 7-0 : these bits, in conjunction with bits 3-0 in register 2e h , set the total line length when the hsizeovr bit is set high . hsize 10-0 must be programmed to be equal to the total number of pixels. the maximum allowable number is 1104 and the default value is 1100.
? 2000-2001 faroudja labs, inc. company confidential 33 rev. 1.04, 1/19/01 FLI2200 address 30 h : inv1 (inv ert ) control register. default value 05 h the eight bits in the inv1 register control the polarities of some signals and other related functions, as shown below: bit 76543 210 mnemonic isyncinv orefinv osyncinv datblnk hdatblnk test imode ccson default value 0 0000 101 isyncinv: this bit is set according to the polarity of the sync inputs, as follows: 0* = normal sync inputs (active high). 1 = inverted sync inputs (active low). orefinv: this controls the polarity of the h and v reference outputs, as follows: 0* = normal reference outputs (active high). 1 = inverted reference outputs (active low). osyncinv: this controls the polarity of the sync outputs, as follows: 0* = normal sync outputs (active high). 1 = inverted sync outputs (active low). datblnk: this controls the passing of ancillary data, as follows: 0* = ancillary data in the vertical blanking interval is not passed. 1 = ancillary data in the vertical blanking interval is passed according to the settings of the hbstartn/p 4-0 /hbstopn/p 5-0 and vbstartn/p 4-0 /vbstopn/p 5-0 bits in registers 17 h -19 h (ntsc) or 27 h -29 h (pal). hdatblnk: this controls the passing of ancillary data in the horizontal blanking interval, as follows: 0* = ancillary data in the horizontal blanking interval is not passed. 1 = ancillary data in the horizontal blanking interval is passed. note that when the deinterlacer is operating in interpolation mode, either adaptively or in stand-alone (nomem) mode, no horizontal data will appear on the interpolated lines, only on the direct lines.. test: this controls the operation of the deinterlacer, as follows: 0 = test mode. 1* = normal operating mode. test: this controls the operation of the deinterlacer, as follows: 0* = normal operating mode. 1 = test mode. ccson: this controls the operation of the cross color suppressor function, as follows: 0 = cross color suppressor disabled. this primarily a test mode. 1* = cross color suppressor enabled. this is the normal operating mode.
FLI2200 rev. 1.04, 1/19/01 34 company confidential ? 2000-2001 faroudja labs, inc. address 31 h : edbl (ed it b lank l eft ) control register. default value e0 h the eight bits in the edbl register control the position of the left hand side of the area of the image used in the bad edit detector, as shown below: bit 76543 210 mnemonic edblnkl 7 edblnkl 6 edblnkl 5 edblnkl 4 edblnkl 3 edblnkl 2 edblnkl 1 edblnkl 0 default value11100 000 edblkl 7-0 : these bits, in conjunction with bit 7 in register 36 h , set the position of the left hand side of the area of the image used in the bad edit detector. the value is the number of pixels from the start of active video. address 32 h : edbr (ed it b lank r ight ) control register. default value 52 h the eight bits in the edbr register control the position of the right hand side of the area of the image used in the bad edit detector, as shown below: bit 76543 210 mnemonic edblnkr 7 edblnkr 6 edblnkr 5 edblnkr 4 edblnkr 3 edblnkr 2 edblnkr 1 edblnkr 0 default value01010 010 edblkr 7-0 : these bits, in conjunction with bits 6 and 5 in register 36 h , set the position of the right hand side of the area of the image used in the bad edit detector. the value is the number of pixels from the start of active video. address 33 h : edbt (ed it b lank t op ) control register. default value 42 h the eight bits in the edbt register control the position of the top of the area of the image used in the bad edit detector, as shown below: bit 76543 210 mnemonic edblnkt 7 edblnkt 6 edblnkt 5 edblnkt 4 edblnkt 3 edblnkt 2 edblnkt 1 edblnkt 0 default value 0 1 0 0 0 0 1 0 edblkt 7-0 : these bits, in conjunction with bit 4 in register 36 h , set the position of the top of the area of the image used in the bad edit detector. the value is the number of pixels from the start of active video. address 34 h : edbbn (ed it b lank b ottom/ n tsc ) control register. default value f4 h the eight bits in the edbbn register control the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic edblnkt 7 edblnkt 6 edblnkt 5 edblnkt 4 edblnkt 3 edblnkt 2 edblnkt 1 edblnkt 0 default value 1 1 1 1 0 1 0 0 edblkbn 7-0 : these bits, in conjunction with bits 3 and 2 in register 36 h , set the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 525 line (ntsc) source. the value is the number of lines from the start of active video.
? 2000-2001 faroudja labs, inc. company confidential 35 rev. 1.04, 1/19/01 FLI2200 address 35 h : edbbp (ed it b lank b ottom/ p al ) control register. default value 58 h the eight bits in the edbbp register control the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic edblnkt 7 edblnkt 6 edblnkt 5 edblnkt 4 edblnkt 3 edblnkt 2 edblnkt 1 edblnkt 0 default value01011 000 edblkbn 7-0 : these bits, in conjunction with bits 3 and 2 in register 36 h , set the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 625 line (pal) source. the value is the number of lines from the start of active video. address 36 h : edbms (ed it b lank m ost significant bits ) control register. default value 66 h the eight bits in the edbms register control the position of the area of the image used in the bad edit detector, as shown below: bit 76543 210 mnemonic edblnkl 8 edblnkr 9 edblnkr 8 edblnkt 8 edblnkbn 9 edblnkbn 8 edblnkbp 9 edblnkbp 8 default value 0 1 1 0 0 1 1 0 edblkl 8 : this bit, in conjunction with bits 7-0 in register 31 h , sets the position of the left hand side of the area of the image used in the bad edit detector. see description of register 31 h for details. edblkr 9-8 : these bits, in conjunction with bits 7-0 in register 32 h , set the position of the right hand side of the area of the image used in the bad edit detector. see description of register 32 h for details. edblkt 8 : this bit, in conjunction with bits 7-0 in register 33 h , sets the position of the top of the area of the image used in the bad edit detector. see description of register 33 h for details. edblkbn 9-8 : these bits, in conjunction with bits 7-0 in register 34 h , set the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 625 line (pal) source. see description of register 34 h for details. edblkbp 9-8 : these bits, in conjunction with bits 7-0 in register 35 h , set the position of the bottom of the area of the image used in the bad edit detector when the input signal comes from a 625 line (pal) source. see description of register 35 h for details. address 37 h : fmbl (f il m b lank l eft ) control register. default value e0 h the eight bits in the fmbl register control the position of the left hand side of the area of the image used in the film mode detector, as shown below: bit 76543 210 mnemonic fmblnkl 7 fmblnkl 6 fmblnkl 5 fmblnkl 4 fmblnkl 3 fmblnkl 2 fmblnkl 1 fmblnkl 0 default value11100 000 fmblkl 7-0 : these bits, in conjunction with bit 7 in register 3c h , set the position of the left hand side of the area of the image used in the film mode detector. the value is the number of pixels from the start of active video.
FLI2200 rev. 1.04, 1/19/01 36 company confidential ? 2000-2001 faroudja labs, inc. address 38 h : fmbr (f il m b lank r ight ) control register. default value 58 h the eight bits in the fmbr register control the position of the right hand side of the area of the image used in the film mode detector, as shown below: bit 76543 210 mnemonic fmblnkr 7 fmblnkr 6 fmblnkr 5 fmblnkr 4 fmblnkr 3 fmblnkr 2 fmblnkr 1 fmblnkr 0 default value01011 000 fmblkr 7-0 : these bits, in conjunction with bits 6 and 5 in register 3c h , set the position of the right hand side of the area of the image used in the film mode detector. the value is the number of pixels from the start of active video. address 39 h : fmbt (f il m b lank t op ) control register. default value 42 h the eight bits in the fmbt register control the position of the top of the area of the image used in the film mode detector, as shown below: bit 76543 210 mnemonic fmblnkt 7 fmblnkt 6 fmblnkt 5 fmblnkt 4 fmblnkt 3 fmblnkt 2 fmblnkt 1 fmblnkt 0 default value 0 1 0 0 0 0 1 0 fmblkt 7-0 : these bits, in conjunction with bit 4 in register 3c h , set the position of the top of the area of the image used in the film mode detector. the value is the number of pixels from the start of active video. address 3a h : fmbbn (f il m b lank b ottom/ n tsc ) control register. default value f4 h the eight bits in the fmbbn register control the position of the bottom of the area of the image used in the film mode detector when the input signal comes from a 525 line (ntsc) source, as shown below: bit 76543 210 mnemonic fmblnkt 7 fmblnkt 6 fmblnkt 5 fmblnkt 4 fmblnkt 3 fmblnkt 2 fmblnkt 1 fmblnkt 0 default value 1 1 1 1 0 1 0 0 fmblkbn 7-0 : these bits, in conjunction with bits 3 and 2 in register 3c h , set the position of the top of the area of the image used in the film mode detector when the input signal comes from a 525 line (ntsc) source. the value is the number of lines from the start of active video. address 3b h : fmbbp (f il m b lank b ottom/ p al ) control register. default value 58 h the eight bits in the fmbbp register control the position of the bottom of the area of the image used in the film mode detector when the input signal comes from a 625 line (pal) source, as shown below: bit 76543 210 mnemonic fmblnkt 7 fmblnkt 6 fmblnkt 5 fmblnkt 4 fmblnkt 3 fmblnkt 2 fmblnkt 1 fmblnkt 0 default value01011 000 fmblkbn 7-0 : these bits, in conjunction with bits 1 and 0 in register 3c h , set the position of the top of the area of the image used in the film mode detector when the input signal comes from a 625 line (pal) source. the value is the number of lines from the start of active video.
? 2000-2001 faroudja labs, inc. company confidential 37 rev. 1.04, 1/19/01 FLI2200 address 3c h : fmbms (f ilm b lank m ost s ignificant bits ) control register. default value 66 h the eight bits in the fmbms register control the position of the area of the image used in the film mode detector, as shown below: bit 76543 210 mnemonic fmblnkl 8 fmblnkr 9 fmblnkr 8 fmblnkt 8 fmblnkbn 9 fmblnkbn 8 fmblnkbp 9 fmblnkbp 8 default value 0 1 1 0 0 1 1 0 edblkl 8 : this bit, in conjunction with bits 7-0 in register 31 h , sets the position of the left hand side of the area of the image used in the film mode detector. see description of register 31 h for details. edblkr 9-8 : these bits, in conjunction with bits 7-0 in register 32 h , set the position of the right hand side of the area of the image used in the film mode detector. see description of register 32 h for details. edblkt 8 : this bit, in conjunction with bits 7-0 in register 33 h , sets the position of the top of the area of the image used in the film mode detector. see description of register 33 h for details. edblkbn 9-8 : these bits, in conjunction with bits 7-0 in register 34 h , set the position of the bottom of the area of the image used in the film mode detector when the input signal comes from a 625 line (pal) source. see description of register 34 h for details. edblkbp 9-8 : these bits, in conjunction with bits 7-0 in register 35 h , set the position of the bottom of the area of the image used in the film mode detector when the input signal comes from a 625 line (pal) source. see description of register 35 h for details. address 3d h through address 54 h : test registers these 24 registers are used purely for test purposes and should not be changed at any time for normal operation. the default values are listed below for reference only. address default value address default value 3d h 14 h 49 h 37 h 3e h 0e h 4a h 1c h 3f h 60 h 4b h 58 h 40 h 05 h 4c h 38 h 41 h 0c h 4d h 00 h 42 h 14 h 4e h 07 h 43 h d5 h 4f h 04 h 44 h 28 h 50 h 14 h 45 h 64 h 51 h 18 h 46 h 08 h 52 h 06 h 47 h 70 h 53 h 30 h 48 h c0 h 54 h 30 h
FLI2200 rev. 1.04, 1/19/01 38 company confidential ? 2000-2001 faroudja labs, inc. address 60 h : pll control register 0. default value 18 h the eight bits in the pll0 register set the pre-divider factor m in the pll, as shown below: bit 76543 210 mnemonic mdiv 7 mdiv 6 mdiv 5 mdiv 4 mdiv 3 mdiv 2 mdiv 1 mdiv 0 default value00011 000 mdiv 7-0 : the pre-divider divides the input pixel clock by the factor m. the requirement is that these bits be used to set the m pre-divider factor in the pll according to the input pixel clock frequency, so that 1 mhz f clkin /m 2 mhz. pdiv should then be set so that 2 (6-pdiv) = mdiv. the values will be: f clkin mdiv ndiv pdiv 8 to 16 mhz 08 h 08 h 3 h to 32 mhz 10 h 10 h 2 h
to 54 mhz 20 h 20 h 1 h note that these registers will be programmed automatically if the pllovr bit, bit 3 in register 62 h , is set low. address 61 h : pll control register 1. default value 30 h the eight bits in the pll1 register set the divider factor n in the pll, as shown below: bit 76543 210 mnemonic ndiv 7 ndiv 6 ndiv 5 ndiv 4 ndiv 3 ndiv 2 ndiv 1 ndiv 0 default value00110 000 ndiv 7-0 : these bits set the feedback division factor n in the pll. this allows the clocks in the FLI2200 to be set up independently for test purposes. for normal operation, ndiv should always be set to be the same as mdiv. see description of register 60 h for more details.
? 2000-2001 faroudja labs, inc. company confidential 39 rev. 1.04, 1/19/01 FLI2200 address 62 h : pll control register 2. default value 02 h the msb is a read-only bit and the other seven bits in the pll2 register control the operation of the clock generation pll, as shown below: bit 7 6 5 4 3 2 1 0 mnemonic lock x disable pbyp pllovr pdiv 2 pdiv 1 pdiv 0 default value r/o x 0 0 0 0 1 0 lock this bit indicates the lock status of the pll, as shown below. it is a read-only (r/o) function. 0 = pll not locked. 1 = pll locked. x: this bit is not used and does not exist physically. disable: this bit allows the pll to be disabled for test purposes, as follows: 0* = pll is enabled. this is the normal mode of operation. 1 = pll is disabled for test purposes. pbyp: this bit allows the pll to be bypassed for test purposes, as follows: 0* = pll is not bypassed. this is the normal mode of operation. 1 = pll is bypassed. pllovr: this bit controls the programming of the pll, as follows: 0* = pll registers are automatically programmed according to the input signal format selected. it will be programmed for a 13.5 mhz input clock frequency (pdiv = 2, ndiv = 30 h , mdiv = 0c h ) unless the d1 (y/cb/cr) input format is selected, in which case it will be programmed for a 27 mhz clock (pdiv = 2, ndiv = 30 h , mdiv = 18 h ). 1 = pll registers at addresses 60 h - 62 h must be programmed manually. pdiv 2-0 : these bits set the post-divider factor p in the pll, determining the clock frequency. pdiv should be set as shown in the description of the pll1 register above, such that 2 (6-pdiv) = mdiv. this will double the clock, as required. see description of register 60 h for more details. address 63 h : output control register 2. default value 00 h the output control register controls some of the output functions, as follows: bit 7 6 5 4 3 2 1 0 mnemonic x x x x x routdis goutdis boutdis default value x x x x x 0 0 0 x: these bits are not used and do not exist physically. r/croutdis: these bits are used to control the r/cr, g/y and b/cb output busses, as follows: g/youtdis: 0 = corresponding bus is active b/cboutdis: 1 = corresponding bus is disabled (set low). this can be used to reduce noise and power consumption when an output bus is not being used in ycb/cr or y/cb/cr modes. }
FLI2200 rev. 1.04, 1/19/01 40 company confidential ? 2000-2001 faroudja labs, inc. address 64 h : clock control register 2. default value 00 h the msb is a read-only bit and the other seven bits in the pll2 register control the operation of the clock generation pll, as shown below: bit 7 6 5 4 3 2 1 0 mnemonic test test invyclk test test test test test default value 0 0 0 0 0 0 0 0 test: these bits all put the FLI2200 into special test modes and should always be set low for normal operation. invyclk: this bit controls the phase of the internal 27 mhz sampling clock used in the iformat = 11x modes, as follows: 0* = sampling clock has same phase as pixclk, samples on falling edgesof pixclk 1 = sampling clock is inverted relative to pixclk, samples on rising edges of pixclk it is recommended that this setting be used in the iformat = 11x modes address 65 h : test register this register is used purely for test purposes and should not be changed at any time for normal operation. the default value is 00 h (for reference only). address 66 h : input hsync delay control register. default value 00 h the input hsync delay control register controls the input horizontal sync timing, as follows: bit 7 6 5 4 3 2 1 0 mnemonic x x x ihsyncdel 4 ihsyncdel 3 ihsyncdel 2 ihsyncdel 1 ihsyncdel 0 default value x x x 0 0 0 0 0 x: these bits are not used and do not exist physically. ihsyncdel 4-0 : these bits set the input horizontal sync timing. the number is a signed, two?s complement value. the adjustment is in 1 pixel increments relative to the default standard timing of this signal as shown in the timing diagrams, as follows: isyncdel 4-0 timing relative to default value 10 h ?16 pixels 00 h * default timing 0f h +15 pixels address 67 h : test. default value 08 h this register is used purely for test purposes and should not be changed at any time for normal operation. the default values is 08 h (for reference only). address 71 h and address 72 h : test registers. default values 00 h these 2 registers are used purely for test purposes and should not be changed at any time for normal operation. the default values are all 00 h (for reference only). address 7e and address 7f h : chip identification registers. default values: 7e h = 41 h , 7f h = 4b h (read only) the eight bits in the idl and idh registers contain the 16-bit chip identification information. register 7e h contains the lower byte and register 7f h contains the upper byte, so that the chip identification number is 4b41 h .
? 2000-2001 faroudja labs, inc. company confidential 41 rev. 1.04, 1/19/01 FLI2200 when the mode pin (pin 46) is set low the FLI2200 operates as a slave device, responding to commands from a master controlling the bus. the protocol is generally i 2 c compatible. between operations the master sets the bus into the idle state, during which the master releases both the clock (scl) and data (sda) lines so that they both go high. all operations commence with a s tart ( s ) command from the master; this is indicated by the master setting the sda line low while the clock is in the high state, as shown in fig. 1. the clock then goes low and an operation begins. all write operations consist of 8-bit (byte) transfers either from or to the master, after which the receiving slave responds with an a cknowledge ( a ) by setting the sda line low for one clock cycle. in the read operation process is similar but the receiver (the master in this case) omits the acknowledge after the data byte is read from the FLI2200. during the course of all operations the sda line will only change while the scl line is low, and should remain stable while scl is high. the master indicates the end of an operation or set of operations with a sto p ( p ) command, indicated a rising edge on sda while scl is high. sets of multiple operations can be executed by means of further s tart commands at the end of each operation with or without a sto p . in all cases, the first byte is always the slave address byte, sent from the master to select the desired device. the settings of the addr 1-0 pins allow the device address of the FLI2200 to be programmed to prevent conflict with the other devices connected to the bus. the slave address can be set to any of the following values, as follows: addr 1-0 device address 0 0 c0/c1 h 0 1 c2/c3 h 1 0 e0/e1 h 1 1 e2/e3 h the seven msbs of the slave address byte are the slave address itself and the lsb is the read/write bit. when the r/w bit is set low (write mode) it indicates that the master is going to transfer more bytes, as shown in fig. 2. the minimum write operation consists of two more bytes, the register address (which selects the register to be written) followed by the data byte for that address. the FLI2200 will respond with an acknowledge after each byte. the master follows these with a sto p command, terminating the operation. multiple registers can also be written sequentially using the auto increment capability of the FLI2200. by sending further bytes of data before the sto p command, as shown in fig. 3, the address is automatically incremented as each sequential byte is written. this is followed by a sto p bit, as before, to terminate the operation. when the r/w bit is set high (read mode) it indicates that the master intends the slave to respond with a data byte from the specified register address. the register address must first be set by writing a register address byte to the FLI2200 (with r/w set high) without an accompanying data byte. the FLI2200 then responds by sending the contents of that register, as shown in fig. 4. the master should terminate the operation at this point by n ot ( n ) issuing an acknowledge, followed by a sto p command. the FLI2200 only has one register containing a read-only bit, the pal status bit, bit 7 in register 07 h . consequently, multiple byte read with auto increment is not supported in the FLI2200. in addition, although it is technically legal under i 2 c protocol to abort a sequence after issuing a s tart followed by a device address, the FLI2200 will not release the bus unless it receives a sto p before another s tart is issued once it is addressed in this way. when the mode pin is set high the FLI2200 will self program from an i 2 c compatible serial memory by reading 128 bytes of data after it is reset. the memory must first be pre-programmed with the necessary programming information. control bus operation and control protocol
FLI2200 rev. 1.04, 1/19/01 42 company confidential ? 2000-2001 faroudja labs, inc. s w a a a p device address register address (n) data byte (n) s w a a a device address register address (n) data byte (n) a p data byte (n+m) figure 2. write mode: single byte write figure 3. write mode: multiple byte write using auto incrementing figure 4. read mode: single byte read control bus operation and control protocol s a a device address register address (n) n p data byte (n) r control bus timing figure 1. control interface timing sb7b6b5b4b3b2b1b0 ack p sd a scl
? 2000-2001 faroudja labs, inc. company confidential 43 rev. 1.04, 1/19/01 FLI2200 electrical characteristics absolute maximum ratings ambient temperature under bias (t a )...................................................................................................... ?40 to +85 c storage temperature (t st )..................................................................................................................... ? 65 to + 150 c voltage on v dd33 pins with respect to ground (v ss )..................................................................................... ?0.5 to + v voltage on v dd25 pins with respect to ground (v ss )..................................................................................... ?0.5 to + v voltage on any pin with respect to ground (v ss )..................................................................................... ?0.3 to +3.6 v input current on any pin during overload condition............................................................................. .. ?10 to +10 ma absolute sum of all input currents during overload condition................................................................... ......... 100 ma power dissipation.............................................................................................................. ................................ 1.75 w note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in FLI2200 rev. 1.04, 1/19/01 44 company confidential ? 2000-2001 faroudja labs, inc. input signal timing input signal timing symbol description min. max. units conditions f pixclk input clock frequency 13.5 mhz iformat 11x, nomem = 0 or nmovr = 1 nomem = 0 27 mhz iformat = 11x, nomem = 0 or nmovr = 1 nomem = 0 37.5 mhz iformat 11x, nomem = 1 or nmovr = 1 nomem = 1 75 mhz iformat = 11x, nomem = 1 or nmovr = 1 nomem = 1 t su input to clock setup 0 nsec. t hd input to clock hold 0 nsec. g/yin 9-0 clkin t su t hd g/yin 9-0 * b/cbin 9-0 * r/crin 9-0 * hsyncrefi cb y cr y cb (10-bit m ode, ifor mat = 11x) * depending on setting of d1insel (30-bit 4:2:2 mode, iformat = 0x1) b/cbin 9-0 r/crin 9-0 b/cbin 9-0 ** r/crin 9-0 ** cb cr cb cr cb (20-bit mode, iformat = 0x0) ** depending on setting of cinsel (except 10-bit mode, ifor mat 11x) sync/ref = 0 (30-bit 4:4:4 mode, iformat = 0x1 or 10x) b/cbin 9-0 r/crin 9-0 invyclk = 0 g/yin 9-0 clkin t su t hd g/yin 9-0 * b/cbin 9-0 * r/crin 9-0 * hsyncrefi cb y cr y cb (10-bit m ode, ifor mat = 11x) * depending on setting of d1insel (30-bit 4:2:2 mode, iformat = 0x1) b/cbin 9-0 r/crin 9-0 b/cbin 9-0 ** r/crin 9-0 ** cb cr cb cr cb (20-bit mode, iformat = 0x0) ** depending on setting of cinsel (except 10-bit mode, ifor mat 11x) sync/ref = 0 (30-bit 4:4:4 mode, iformat = 0x1 or 10x) b/cbin 9-0 r/crin 9-0 invyclk = 0
? 2000-2001 faroudja labs, inc. company confidential 45 rev. 1.04, 1/19/01 FLI2200 output signal timing output signal timing symbol description min. nom. max. units conditions f yclkout output luma clock frequency 75 mhz t pdo clock to output delay ?3 +3 nsec. yc l ko cclko hrefo cb cr cb cr cb r/crout 9-0 b/cbout 9-0 (30-bit 4:2:2 mode, oformat = 0x1) t pdo cb y cr y b/cbout 9-0 * r/crout 9-0 * (20-bit m ode, ofor mat = 0x0) * depending on setting of coutsel g/yout 9-0 (except 10-bit mode, ofor mat 11x) g/yout 9-0 (10-bit m ode, ofor mat = 11x) (30-bit 4:4:4 mode, oformat = 0x1 or 10x) r/crout 9-0 b/cbout 9-0 me mc l ko cb y cr y cb y cr yc l ko cclko hrefo cb cr cb cr cb r/crout 9-0 b/cbout 9-0 (30-bit 4:2:2 mode, oformat = 0x1) t pdo cb y cr y b/cbout 9-0 * r/crout 9-0 * (20-bit m ode, ofor mat = 0x0) * depending on setting of coutsel g/yout 9-0 (except 10-bit mode, ofor mat 11x) g/yout 9-0 (10-bit m ode, ofor mat = 11x) (30-bit 4:4:4 mode, oformat = 0x1 or 10x) r/crout 9-0 b/cbout 9-0 me mc l ko cb y cr y cb y cr
FLI2200 rev. 1.04, 1/19/01 46 company confidential ? 2000-2001 faroudja labs, inc. applications information deinterlacing video signals: optimal solutions for optimal images under different conditions there are several different conditions that exist in video signals that require different approaches to deinterlacing. the first and most obvious is a moving image (or portion of an image) versus a still image (or portion of an image). it is fairly obvious that still images can be deinterlaced simply by interleaving the odd and even fields, i.e., forming a full frame of 525 (in the case of ntsc) lines by taking the 262.5 lines from the odd field 1, 3, 5, etc. and interleaving them with the 262.5 lines from the even field (2, 4, 6, etc.) to form a complete frame of 525 lines (1, 2, 3, 4, etc.) and displaying it at the field rate, i.e., 59.94 hz. however, if anything in the image moves between the odd and even fields the results will be disastrous! an example is shown in fig. a1, below, where the car is moving from left to right. if the car is moving at 60 mph it will have moved 1.5 feet between the frames. (a) odd field: time = t fig. a1. the result of interleaving fields containing motion. (a) even field: time = t + 1 / 60 sec. (c) odd and even fields interleaved the way to deal with a moving image is to deal with the fields independently and generate the missing lines in each field by interpolation. there are several way in which this can be done, the easiest being to assume that the image is always going to be in motion, and interpolate all the time. this, of course, results in an image which appears to very soft when (and where) there is no motion as a result of the fact that the true vertical resolution has been reduced, relative to the original image. the second method is to use a motion detector of some kind to detect whether anything has moved from frame to frame and to use this to control the system: interpolate when motion is detected, interleave when no motion is detected. although it is possible to implement a motion detector simply by computing a metric for each field and comparing it with that for the same field from the previous frame, this only allows the choice of interleave versus interpolate to be made on a field by field basis. in addition, unless a field memory (delay) is used, the metric for the current field cannot be computed until the field has already been displayed. this is an extremely undesirable condition since the motion/no motion condition on a per field basis changes continuously. even when the field delay is used, this method is far from optimum because any motion anywhere in the image will cause the system to switch into interpolate mode, resulting in soft images in areas of the picture containing no motion, a very common condition. a much better way is to compute a motion metric on a pixel by pixel basis, and this is the method used in the FLI2200. the motion detector is frame based and compares the luma value of the current pixel and the same pixel in the previous frame. this is done in both the odd and even fields to generate a motion vector which is then used to switch the signal processing between field interleave and interpolation modes on a pixel by pixel basis. in this way, non-moving parts of the picture, where sharpness is readily detected by the viewer, will not be interpolated and will have maximum sharpness. conversely, moving parts of the picture, where sharpness is not easily detected by the viewer, will be interpolated to avoid motion artifacts. the most common method of implementing the interpolation function is to use a 2-line memory and generate the interpolated pixels from the pixel above (previous line) and the pixel below (next line). this implementation can be improved by using more ?previous? and ?next? lines to implement a higher order interpolating filter, giving slightly sharper images. however, no matter how complex the interpolating filter is, it always operates on the basis that the current pixel is
? 2000-2001 faroudja labs, inc. company confidential 47 rev. 1.04, 1/19/01 FLI2200 odd field even field odd field even field odd field even field odd field even field odd field even field odd 1+ even 1 odd 1+ even 1 odd 1+ even 1 odd 2+ even 2 odd 2+ even 2 odd 3+ even 3 odd 3+ even 3 odd 3+ even 3 odd 4+ even 4 movie frame 1 movie frame 2 movie frame 3 movie frame 4 24 hz 60 hz interlaced 60 hz progressive 1 / 6 sec. fig. a3. ?3:2 pulldown? sequence used in converting 24 fps film to ntsc. fig. a2. conventional vertical interpolation on diagonal edges (l) versus diagonal interpolation (r) related to the pixels above and below it, which is completely untrue of diagonal edges. whenever an edge is not vertical, the current pixel is related to those diagonally above and below it in a relationship which depends on the angle of the edge, e.g., if the angle is 45, the relationship is ?one up and one across? and ?one down and one across?. with other angles becomes more complex and will involve non-integer relationships. consequently, it is extremely difficult to implement such a ?diagonal interpolation? algorithm, but this has been achieved in the FLI2200. this new algorithm (patent pending) computes and tracks the angles of edges and uses this information to optimally fill in the missing pixels. it greatly improves the quality of moving images, particularly those in fairly slow motion, such as the waving flag shown in fig. a2 below, by eliminating the ?jaggies? conventionally generated by interpolation. deinterlacing images which originated from progressive scan sources, including film whenever an interlaced image is generated from a progressively scanned image (where the original frame rate equals the field rate after interlacing) the resulting odd and even field pairs will originate from the same frame and, by definition, there will be no motion between them since the images occurred at the same point in time. a special instance of this is the conversion of film to video in a telecin machine. there are two types of telecin machines. the first is the one used to convert 24 fps film to 60 field/sec. (30 fps) video, i.e., ntsc. since it is not practical to run a 24 fps film at 30 fps the technique used is called ?3:2 pulldown?, in which each film frame is alternately mapped into three video fields and two video fields. the resulting ratio of two film frames to five video fields matches the rate of the film precisely to the 59.94 fields/sec. rate of the video when the film is run at 23.976 fps. the mapping sequence is shown in fig. a3, below. note that there are alternating consecutive pairs of odd fields and even fields originating from the same film frame. this makes it possible for a frame based motion detector to synchronize a state machine to this sequence (us patent 4,982,280) and match the odd and even fields originating from the same frame. in this way the video can be deinterlaced by interleaving these fields at all times, regardless of motion, resulting in the ultimate image quality. the second type of telecin is the ?one film frame to one pair of video fields? type (sometimes referred to as ?2:2 pulldown?). this type is primarily used to convert conventional 24 frame/sec. (fps) film to 50 field/sec. video, i.e., pal. in this case the film is actually run at 25 fps. the 4% speed increase is not noticeable in the video, but those with the sense of ?perfect pitch? can detect the raised pitch of the sound track. this type of telecin is also used to convert 30 fps film to ntsc video. although there are no pairs of the same field (odd or even) originating form the same film frame in the resulting video it is still possible to detect the sequence by using a field based motion detector and use this to match pairs of fields originating from the same film frame, allowing them to be interleaved, again resulting in the ultimate image quality.
FLI2200 rev. 1.04, 1/19/01 48 company confidential ? 2000-2001 faroudja labs, inc. the video resulting from both types of telecin machines has one problem: if the video is edited, it is possible for the sequence to be broken. in the 2:2 pulldown case there are four possibilities: 1. good cut (at video frame start) 2. bad cut (mid frame, between odd and even fields) 3. good restart (at frame start) 4. bad restart (mid frame) both the good cut/good restart and bad cut/bad restart combinations will result in the preservation of the sequence, although the bad cut/bad restart combination will result in a single bad frame (odd and even fields did not originate from the same film frame). both the good cut/bad restart and bad cut/good restart combinations will break the sequence and result in bad video until the ?film mode detect? state machine is resequenced, which typically takes up to 12 frames. note that if the editor is frame based, only the good cut/good restart combination will occur. the situation with 3:2 pulldown derived video is significantly worse. even with a frame based editor there are 25 possible cases since the transfer sequence repeats over a period of five video frames, resulting in five possible cut points and five possible restart points. only two of these will result in good edits, the other 23 resulting in the ?film mode detect? state machine going out of sync and having to be resequenced. thus it is virtually guaranteed that a video edit in ntsc will cause the system to lose sync, resulting in very bad deinterlacing artifacts until it is resequenced. to minimize the consequences of bad edits, the FLI2200 incorporates a bad edit detector. this will detect even the single bad frame resulting from the bad/bad combination in pal and, since it operates in a ?look forward? mode, will cause the system to switch out of film mode before even a single bad field is displayed. the resulting lower quality video mode is preferable to the alternative, given the pixel by pixel motion handling and the high quality of the diagonal interpolation, even in the single bad frame case. fli2000 FLI2200 b/b-y/ ccirin 9-0 pixclk b/b-y/ ccir/c 9-0 mclkout/ 2m clko ut interfacing the FLI2200 to video and mpeg decoders with itu-r bt656 outputs interfacing the FLI2200 to an 8- or 10-bit parallel itu-r bt656 (d1) signal source, suchas the fli2000, is very simple since the FLI2200 can decode these signals. since these signals include timing information in the horizontal and vertical banking intervals, no other syncs are required, so that the only interconnections required are the 10-bit data and the clock, as shown in fig. a4. the input signal format can be controlled by means of the iformat 2-0 pins (pins 56-58). the correct setting for the itu-r bt656 input mode is 110. this setting can be overridden by the ifmtovr bit, bit 3 in register 00 h , allowing this function to be set or changed via the control bus if preferred. please refer to the description of register 00 h for details. it is recommended that the interconnections be kept short since the operating speed in this mode is 27 mhz. fig. a4. interfacing the FLI2200 to the fli2000 ntsc/pal decoder using the itu-r bt656 (d1) format.
? 2000-2001 faroudja labs, inc. company confidential 49 rev. 1.04, 1/19/01 FLI2200 input modes and busses the FLI2200 has very flexible input and output controls that make it very easy to use in all applpications. the input formats and modes are summarized in the table below. for reference, the signals are as follows: input signals on busses iformat 2-0 ifmtovr iformat 2-0 cinsel d1insel 1-0 g/yin b/cbin r/crin clock rate/mode 0 0 0 0 x 0 x y cb/cr x (13.5 mhz, 4:2:2) 0 0 0 0 x 1 x y x cb/cr (13.5 mhz, 4:2:2) 0 0 1 0 x x x y cb cr (13.5/6.75 mhz, 4:2:2) 0 1 0 0 x 0 x y pb/pr x (13.5 mhz, 4:2:2) 0 1 0 0 x 1 x y x pb/pr (13.5 mhz, 4:2:2) 0 1 1 0 x x x y pb pr (13.5/6.75 mhz, 4:2:2) 1 0 0 0 x x x g b r (13.5 mhz, 4:4:4) 1 0 1 0 x x x g b r (13.5 mhz, 4:4:4) 1 1 0 0 x x 0 0 y/cb/cr x x (27 mhz, embedded timing) 1 1 0 0 x x 0 1 y/cb/cr x x (27 mhz, embedded timing) 1 1 0 0 x x 1 0 x y/cb/cr (27 mhz, embedded timing) 1 1 0 0 x x 1 1 x x y/cb/cr (27 mhz, embedded timing) 1 1 1 0 x x 0 0 y/cb/cr x x (27 mhz, separate timing/syncs) 1 1 1 0 x x 0 1 y/cb/cr x x (27 mhz, separate timing/syncs) 1 1 1 0 x x 1 0 x y/cb/cr x (27 mhz, separate timing/syncs) 1 1 1 0 x x 1 1 x x y/cb/cr (27 mhz, separate timing/syncs) x 1 0 0 0 0 x y cb/cr x (13.5 mhz, 4:2:2) x 1 0 0 0 1 x y x cb/cr (13.5 mhz, 4:2:2) x 1 0 0 1 x x y cb cr (13.5/6.75 mhz, 4:2:2) x 1 0 0 1 0 x y pb/pr x (13.5 mhz, 4:2:2) x 1 0 1 0 1 x y x pb/pr (13.5 mhz, 4:2:2) x 1 0 1 1 x x y pb pr (13.5/6.75 mhz, 4:2:2) x 1 1 0 0 x x g b r (13.5 mhz, 4:4:4) x 1 1 0 1 x x g b r (13.5 mhz, 4:4:4) x 1 1 1 0 x 0 0 y/cb/cr x x (27 mhz, embedded timing) x 1 1 1 0 x 0 1 y/cb/cr x x (27 mhz, embedded timing) x 1 1 1 0 x 1 0 x y/cb/cr (27 mhz, embedded timing) x 1 1 1 0 x 1 1 x x y/cb/cr (27 mhz, embedded timing) x 1 1 1 1 x 0 0 y/cb/cr x x (27 mhz, separate timing/syncs) x 1 1 1 1 x 0 1 y/cb/cr x x (27 mhz, separate timing/syncs) x 1 1 1 1 x 1 0 x y/cb/cr x (27 mhz, separate timing/syncs) x 0 1 1 1 x 1 1 x x y/cb/cr (27 mhz, separate timing/syncs) iformat 2-0 pins are pins 56-58 iformat 2-0 are bits 2-0 in register 00 h ifmtovr is bit 3 in register 00 h cinsel is bit 6 in register 08 h d1insel 1-0 are bits 4-3 in register 08 h
FLI2200 rev. 1.04, 1/19/01 50 company confidential ? 2000-2001 faroudja labs, inc. output modes and busses the FLI2200 has very flexible input and output controls that make it very easy to use in all applications. the output formats and modes are summarized in the table below. for reference, the signals are as follows: input signals on busses oformat 2-0 ofmtovr oformat 2-0 coutsel g/yout b/cbout r/crout clock rate/mode 0 0 0 0 x x g b r (27 mhz, 4:4:4) 0 0 1 0 x x y cb cr (27/13.5 mhz, 4:2:2) 0 1 0 0 x 0 y cb/cr y/cb/cr (27/54 mhz, 4:2:2, separate timing/syncs) 0 1 0 0 x 1 y y/cb/cr cb/cr (27/54 mhz, 4:2:2, separate timing/syncs) 0 1 1 0 x 0 y cb/cr y/cb/cr (27/54 mhz, 4:2:2, embedded timing) 0 1 1 0 x 1 y y/cb/cr cb/cr (27/54 mhz, 4:2:2, embedded timing) 1 0 0 0 x x y pb pr (27/13.5 mhz, 4:2:2) 1 0 1 0 x 0 y pb/pr x (27 mhz, 4:2:2) 1 0 1 0 x 1 y x pb/pr (27 mhz, 4:2:2) 1 1 0 0 x x y cb cr (27 mhz, 4:4:4) 1 1 1 0 x x x x x test mode only x 1 0 0 0 x g b r (27 mhz, 4:4:4) x 1 0 0 1 x y cb cr (27/13.5 mhz, 4:2:2) x 1 0 1 0 0 y cb/cr y/cb/cr (27/54 mhz, 4:2:2, separate timing/syncs) x 1 0 1 0 1 y y/cb/cr cb/cr (27/54 mhz, 4:2:2, separate timing/syncs) x 1 0 1 1 0 y cb/cr y/cb/cr (27/54 mhz, 4:2:2, embedded timing) x 1 0 1 1 1 y y/cb/cr cb/cr (27/54 mhz, 4:2:2, embedded timing) x 1 1 0 0 x y pb pr (27/13.5 mhz, 4:2:2) x 1 1 0 1 0 y pb/pr x (27 mhz, 4:2:2) x 1 1 0 1 1 y x pb/pr (27 mhz, 4:2:2) x 1 1 1 0 x y cb cr (27 mhz, 4:4:4) x 1 1 1 1 x x x x test mode only oformat 2-0 pins are pins 59-61 oformat 2-0 are bits 2-0 in register 07 h ofmtovr is bit 3 in register 07 h coutsel is bit 5 in register 08 h
? 2000-2001 faroudja labs, inc. company confidential 51 rev. 1.04, 1/19/01 FLI2200 millimeters inches ref. min. typ. max. min. typ. max. a 1.40 1.60 0.055 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.003 0.008 d 24.0 0.945 e 24.0 0.945 e 0.50 0.020 h d 26.0 1.024 h e 26.0 1.024 l 0.45 0.60 0.75 0.018 0.024 0.029 l1 1.00 0.039 z d 1.25 0.05 z e 1.25 0.05 0 7 0 7 note: inch dimensions are derived from the original metric dimensions and may be approximate. package dimensions
FLI2200 rev. 1.04, 1/19/01 52 company confidential ? 2000-2001 faroudja labs, inc. for more information, write or call: faroudja laboratories, a division of sage, inc., 750 palomar avenue, sunnyvale, ca 94086 phone: (408) 735-1492 fax: (408) 735-1571 http://www.faroudja.com is a registered trademark of faroudja laboratories, inc. (fli). fli does not convey any license under its patents for the use of this product.

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